diff options
| author | Bernd Schmidt <bernds@codesourcery.com> | 2008-03-26 14:50:52 +0000 |
|---|---|---|
| committer | Bernd Schmidt <bernds@codesourcery.com> | 2008-03-26 14:50:52 +0000 |
| commit | b21c9cb44026744541fb5e8f8ede89c6c2220c6d (patch) | |
| tree | e5eb6fb610366fe01702864ec22e7209bfda179e /gas/testsuite | |
| parent | a5defcdc217d048f8a7e1815d16986d87b1c2148 (diff) | |
| download | gdb-b21c9cb44026744541fb5e8f8ede89c6c2220c6d.zip gdb-b21c9cb44026744541fb5e8f8ede89c6c2220c6d.tar.gz gdb-b21c9cb44026744541fb5e8f8ede89c6c2220c6d.tar.bz2 | |
opcodes:
From Robin Getz <robin.getz@analog.com>
* bfin-dis.c (bu32): Typedef.
(enum const_forms_t): Add c_uimm32 and c_huimm32.
(constant_formats[]): Add uimm32 and huimm16.
(fmtconst_val): New.
(uimm32): Define.
(huimm32): Define.
(imm16_val): Define.
(luimm16_val): Define.
(struct saved_state): Define.
(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
(get_allreg): New.
(decode_LDIMMhalf_0): Print out the whole register value.
gas/testsuite:
From Jie Zhang <jie.zhang@analog.com>
* gas/bfin/load.d: Update.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/bfin/load.d | 20 |
2 files changed, 15 insertions, 10 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index b5b46bd..8c12810 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com> + + From Jie Zhang <jie.zhang@analog.com> + * gas/bfin/load.d: Update. + 2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/zarch-z10.d: New file. diff --git a/gas/testsuite/gas/bfin/load.d b/gas/testsuite/gas/bfin/load.d index 07af139..b97142b 100644 --- a/gas/testsuite/gas/bfin/load.d +++ b/gas/testsuite/gas/bfin/load.d @@ -5,17 +5,17 @@ Disassembly of section .text: 00000000 <load_immediate>: - 0: 17 e1 ff ff M3.L=ffff.* - 4: 1a e1 fe ff B2.L=fffe.* + 0: 17 e1 ff ff M3.L=0xffff.* + 4: 1a e1 fe ff B2.L=0xfffe.* 8: 0e e1 00 00 SP.L=0.* - c: 0f e1 dc fe FP.L=fedc.* - 10: 40 e1 02 00 R0.H=0x2; - 14: 4d e1 20 00 P5.H=20.* - 18: 52 e1 04 f2 I2.H=f204.* - 1c: 59 e1 40 00 B1.H=40.* - 20: 5c e1 ff ff L0.H=ffff.* - 24: 45 e1 00 00 R5.H=0x0; - 28: 5a e1 00 00 B2.H=0 <load_immediate>; + c: 0f e1 dc fe FP.L=0xfedc.* + 10: 40 e1 02 00 R0.H=0x2.* + 14: 4d e1 20 00 P5.H=0x20.* + 18: 52 e1 04 f2 I2.H=0xf204.* + 1c: 59 e1 40 00 B1.H=0x40.* + 20: 5c e1 ff ff L0.H=0xffff.* + 24: 45 e1 00 00 R5.H=0x0.* + 28: 5a e1 00 00 B2.H=0x0.* 2c: 8f e1 20 ff FP=ff20.* 30: 9e e1 20 00 L2=20.* 34: 85 e1 00 00 R5=0 <load_immediate>\(Z\); |