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| author | Jan Beulich <jbeulich@suse.com> | 2022-03-04 13:37:59 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2022-03-04 13:37:59 +0100 |
| commit | 7919e5667cf6607a3d7e28b1fa7f15f3c49a4e55 (patch) | |
| tree | 28d8cd75aa781911c522ef5e56d677bfdc525c2d /gas/testsuite | |
| parent | 6a778a2100901f665ed087d069e5c962bd4c93d7 (diff) | |
| download | gdb-7919e5667cf6607a3d7e28b1fa7f15f3c49a4e55.zip gdb-7919e5667cf6607a3d7e28b1fa7f15f3c49a4e55.tar.gz gdb-7919e5667cf6607a3d7e28b1fa7f15f3c49a4e55.tar.bz2 | |
RISC-V: make .insn actually work for 64-bit insns
Presently in this case, due to an undefined behavior shift, at least
with x86 cross builds I'm observing:
Error: value conflicts with instruction length `8,0x0000003f'
Eliminate the UB and extend the respective testcase.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/riscv/insn.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/insn.s | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d index e55030e..b5780f4 100644 --- a/gas/testsuite/gas/riscv/insn.d +++ b/gas/testsuite/gas/riscv/insn.d @@ -71,5 +71,9 @@ Disassembly of section .text: [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 [^:]+:[ ]+0001[ ]+nop [^:]+:[ ]+00000013[ ]+nop +[^:]+:[ ]+001f 0000 0000[ ].* +[^:]+:[ ]+0000003f 00000000[ ].* [^:]+:[ ]+0001[ ]+nop [^:]+:[ ]+00000013[ ]+nop +[^:]+:[ ]+001f 0000 0000[ ].* +[^:]+:[ ]+0000003f 00000000[ ].* diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s index e47f529..ec41acb 100644 --- a/gas/testsuite/gas/riscv/insn.s +++ b/gas/testsuite/gas/riscv/insn.s @@ -56,5 +56,9 @@ target: .insn 0x0001 .insn 0x00000013 + .insn 0x0000001f + .insn 0x0000003f .insn 0x2, 0x0001 .insn 0x4, 0x00000013 + .insn 6, 0x0000001f + .insn 8, 0x0000003f |