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| author | Alexandre Oliva <oliva@adacore.com> | 2020-03-04 17:28:46 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2020-03-04 17:28:46 +0000 |
| commit | 749479c8d3b63c9075d2fabf4b87b1f7109608b6 (patch) | |
| tree | ea0bf41a6d7fb0dd11a33e930893a96adb2a9f38 /gas/testsuite | |
| parent | 440cf44eb0f70830b8d8ac35289f84129c7a35c1 (diff) | |
| download | gdb-749479c8d3b63c9075d2fabf4b87b1f7109608b6.zip gdb-749479c8d3b63c9075d2fabf4b87b1f7109608b6.tar.gz gdb-749479c8d3b63c9075d2fabf4b87b1f7109608b6.tar.bz2 | |
Generate a warning in the ARM assembler if a PC-relative thumb load instruction is detected in a section with insufficient alignment.
* config/tc-arm.c (md_apply_fix): Warn if a PC-relative load is
detected in a section which does not have at least 4 byte
alignment.
* testsuite/gas/arm/armv8-ar-it-bad.s: Add alignment directive.
* testsuite/gas/arm/ldr-t.s: Likewise.
* testsuite/gas/arm/sp-pc-usage-t.s: Likewise.
* testsuite/gas/arm/sp-pc-usage-t.d: Finish test at end of
disassembly, ignoring any NOPs that may have been inserted because
of section alignment.
* testsuite/gas/arm/ldr-t.d: Likewise.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/arm/armv8-ar-it-bad.s | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/ldr-t.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/ldr-t.s | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/sp-pc-usage-t.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/sp-pc-usage-t.s | 3 |
5 files changed, 8 insertions, 6 deletions
diff --git a/gas/testsuite/gas/arm/armv8-ar-it-bad.s b/gas/testsuite/gas/arm/armv8-ar-it-bad.s index 9864bf8..3a67e8d 100644 --- a/gas/testsuite/gas/arm/armv8-ar-it-bad.s +++ b/gas/testsuite/gas/arm/armv8-ar-it-bad.s @@ -1,6 +1,6 @@ -.syntax unified - -.thumb + .syntax unified + .thumb + .align 2 @ Wide instruction in IT block is deprecated. it eq ldrdeq r0, [r1] diff --git a/gas/testsuite/gas/arm/ldr-t.d b/gas/testsuite/gas/arm/ldr-t.d index ddcd612..9763739 100644 --- a/gas/testsuite/gas/arm/ldr-t.d +++ b/gas/testsuite/gas/arm/ldr-t.d @@ -34,4 +34,4 @@ Disassembly of section [^>]+: 0+4e <[^>]+> f8c1 100a str.w r1, \[r1, #10\] 0+52 <[^>]+> f842 1f0a str.w r1, \[r2, #10\]! 0+56 <[^>]+> 50d1 str r1, \[r2, r3\] - +#pass diff --git a/gas/testsuite/gas/arm/ldr-t.s b/gas/testsuite/gas/arm/ldr-t.s index 4aaecdf..ba3b1e0 100644 --- a/gas/testsuite/gas/arm/ldr-t.s +++ b/gas/testsuite/gas/arm/ldr-t.s @@ -3,6 +3,7 @@ .thumb .global foo foo: + .align 4 @ldr-immediate @!wback && (n == t) diff --git a/gas/testsuite/gas/arm/sp-pc-usage-t.d b/gas/testsuite/gas/arm/sp-pc-usage-t.d index 6dedc00..c9b0800 100644 --- a/gas/testsuite/gas/arm/sp-pc-usage-t.d +++ b/gas/testsuite/gas/arm/sp-pc-usage-t.d @@ -79,4 +79,4 @@ Disassembly of section .text: 000000f6 <foo\+0xf6> bf00 nop 000000f8 <foo\+0xf8> bf00 nop 000000fa <foo\+0xfa> bf00 nop - +#pass diff --git a/gas/testsuite/gas/arm/sp-pc-usage-t.s b/gas/testsuite/gas/arm/sp-pc-usage-t.s index 6cfebed..70bf0d9 100644 --- a/gas/testsuite/gas/arm/sp-pc-usage-t.s +++ b/gas/testsuite/gas/arm/sp-pc-usage-t.s @@ -3,7 +3,8 @@ .text .thumb .global foo -foo: +foo: + .align 4 @ Section A6.1.3 "Use of 0b1101 as a register specifier". @ R13 as the source or destination register of a mov instruction. |