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| author | Jan Beulich <jbeulich@suse.com> | 2020-02-12 16:20:56 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2020-02-12 16:20:56 +0100 |
| commit | 6c0946d0d28d787b166cae3c2ebc2cb309c4f5a2 (patch) | |
| tree | 6a01cbf5a6b3755e26b6d68fcddb99214f00b6dd /gas/testsuite | |
| parent | ddb56fe60054be3463ba30dde8d6c41d641dee01 (diff) | |
| download | gdb-6c0946d0d28d787b166cae3c2ebc2cb309c4f5a2.zip gdb-6c0946d0d28d787b166cae3c2ebc2cb309c4f5a2.tar.gz gdb-6c0946d0d28d787b166cae3c2ebc2cb309c4f5a2.tar.bz2 | |
x86: correct VFPCLASSP{S,D} operand size handling
With AVX512VL disabled (e.g. when writing code for the Knights family
of processors) these insns aren't ambiguous when used with a memory
source, and hence should be accepted without suffix or operand size
specifier. When AVX512VL is enabled, to be consistent with this as
well as other ambiguous operand size handling it would seem better to
just warn about the ambiguity in AT&T mode, and still default to 512-bit
operands (on the assumption that the code may have been written without
AVX512VL in mind yet), but it was requested to leave AT&T syntax mode
alone here.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/i386/avx512dq-inval.l | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/avx512dq-inval.s | 9 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/noavx512-2.l | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/noavx512-2.s | 4 |
4 files changed, 22 insertions, 2 deletions
diff --git a/gas/testsuite/gas/i386/avx512dq-inval.l b/gas/testsuite/gas/i386/avx512dq-inval.l index 1533fb4..e8a0274 100644 --- a/gas/testsuite/gas/i386/avx512dq-inval.l +++ b/gas/testsuite/gas/i386/avx512dq-inval.l @@ -11,3 +11,7 @@ .*:[0-9]*: Error:.* `vpinsrq' .* .*:[0-9]*: Error:.* `vpinsrq' .* .*:[0-9]*: Error:.* `vpinsrq' .* +.*:[0-9]*: Error:.* `vfpclasspd' +.*:[0-9]*: Error:.* `vfpclassps' +.*:[0-9]*: Error:.* `vfpclasspd' +.*:[0-9]*: Error:.* `vfpclassps' diff --git a/gas/testsuite/gas/i386/avx512dq-inval.s b/gas/testsuite/gas/i386/avx512dq-inval.s index 7f0f024..facc5f3 100644 --- a/gas/testsuite/gas/i386/avx512dq-inval.s +++ b/gas/testsuite/gas/i386/avx512dq-inval.s @@ -1,4 +1,4 @@ -# Check AVX512DQ instructions not to be accepted outside of 64-bit mode +# Check AVX512DQ instructions not to be accepted (in part only outside of 64-bit mode) .text _start: @@ -20,3 +20,10 @@ _start: vpinsrq xmm0, xmm0, qword ptr [eax], 0 {evex} vpinsrq xmm0, xmm0, qword ptr [eax], 0 + vfpclasspd k0, [eax], 0 + vfpclassps k0, [eax], 0 + + .att_syntax prefix + + vfpclasspd $0, (%eax), %k0 + vfpclassps $0, (%eax), %k0 diff --git a/gas/testsuite/gas/i386/noavx512-2.l b/gas/testsuite/gas/i386/noavx512-2.l index bdaaab2..56d1aaa 100644 --- a/gas/testsuite/gas/i386/noavx512-2.l +++ b/gas/testsuite/gas/i386/noavx512-2.l @@ -101,5 +101,10 @@ GAS LISTING .* [ ]*50[ ]+F5 [ ]*51[ ]+\?\?\?\? 660F58F4 addpd %xmm4, %xmm6 [ ]*52[ ]+ -[ ]*53[ ]+\?\?\?\? 0F1F00 \.p2align 4 +[ ]*[1-9][0-9]*[ ]+\.intel_syntax noprefix +[ ]*[1-9][0-9]*[ ]+\?\?\?\? 62F3FD48 vfpclasspd k0, \[eax], 0 +[ ]*[1-9][0-9]*[ ]+660000 +[ ]*[1-9][0-9]*[ ]+\?\?\?\? 62F37D48 vfpclassps k0, \[eax], 0 +[ ]*[1-9][0-9]*[ ]+660000 +[ ]*[1-9][0-9]*[ ]+ #pass diff --git a/gas/testsuite/gas/i386/noavx512-2.s b/gas/testsuite/gas/i386/noavx512-2.s index b9ef95c..437dc04 100644 --- a/gas/testsuite/gas/i386/noavx512-2.s +++ b/gas/testsuite/gas/i386/noavx512-2.s @@ -50,4 +50,8 @@ pabsb %xmm5, %xmm6 addpd %xmm4, %xmm6 + .intel_syntax noprefix + vfpclasspd k0, [eax], 0 + vfpclassps k0, [eax], 0 + .p2align 4 |