[PATCH 29/57][Arm][GAS] Add support for MVE instructions: vqdmullt and vqdmullb

gas/ChangeLog:
2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (enum operand_parse_code): Add new operand.
	(parse_operands): Handle new operand.
	(do_mve_vqdmull): New encoding function.
	(insns): Add entry for MVE mnemonics.
	* testsuite/gas/arm/mve-vqdmull-bad.d: New test.
	* testsuite/gas/arm/mve-vqdmull-bad.l: New test.
	* testsuite/gas/arm/mve-vqdmull-bad.s: New test.

3 files changed, 121 insertions, 0 deletions

diff --git a/gas/testsuite/gas/arm/mve-vqdmull-bad.d b/gas/testsuite/gas/arm/mve-vqdmull-bad.d
new file mode 100644
index 0000000..4eb6fb2
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmull-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VQDMULLT and VQDMULLB instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vqdmull-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vqdmull-bad.l b/gas/testsuite/gas/arm/mve-vqdmull-bad.l
new file mode 100644
index 0000000..1ddc335
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmull-bad.l
@@ -0,0 +1,61 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vqdmullt.s8 q0,q1,q2'
+[^:]*:11: Error: bad type in SIMD instruction -- `vqdmullt.u8 q0,q1,q2'
+[^:]*:12: Error: bad type in SIMD instruction -- `vqdmullt.i16 q0,q1,q2'
+[^:]*:13: Error: bad type in SIMD instruction -- `vqdmullt.s64 q0,q1,q2'
+[^:]*:14: Error: bad type in SIMD instruction -- `vqdmullb.s8 q0,q1,q2'
+[^:]*:15: Error: bad type in SIMD instruction -- `vqdmullb.u8 q0,q1,q2'
+[^:]*:16: Error: bad type in SIMD instruction -- `vqdmullb.i16 q0,q1,q2'
+[^:]*:17: Error: bad type in SIMD instruction -- `vqdmullb.s64 q0,q1,q2'
+[^:]*:18: Error: bad type in SIMD instruction -- `vqdmullt.s8 q0,q1,r2'
+[^:]*:19: Error: bad type in SIMD instruction -- `vqdmullt.u8 q0,q1,r2'
+[^:]*:20: Error: bad type in SIMD instruction -- `vqdmullt.i16 q0,q1,r2'
+[^:]*:21: Error: bad type in SIMD instruction -- `vqdmullt.s64 q0,q1,r2'
+[^:]*:22: Error: bad type in SIMD instruction -- `vqdmullb.s8 q0,q1,r2'
+[^:]*:23: Error: bad type in SIMD instruction -- `vqdmullb.u8 q0,q1,r2'
+[^:]*:24: Error: bad type in SIMD instruction -- `vqdmullb.i16 q0,q1,r2'
+[^:]*:25: Error: bad type in SIMD instruction -- `vqdmullb.s64 q0,q1,r2'
+[^:]*:26: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:27: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:28: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:29: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:30: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:31: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:32: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:33: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:34: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:35: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:41: Error: syntax error -- `vqdmullteq.s32 q0,q1,q2'
+[^:]*:42: Error: syntax error -- `vqdmullteq.s32 q0,q1,q2'
+[^:]*:44: Error: syntax error -- `vqdmullteq.s32 q0,q1,q2'
+[^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmulltt.s32 q0,q1,q2'
+[^:]*:47: Error: instruction missing MVE vector predication code -- `vqdmullt.s32 q0,q1,q2'
+[^:]*:49: Error: syntax error -- `vqdmullbeq.s32 q0,q1,q2'
+[^:]*:50: Error: syntax error -- `vqdmullbeq.s32 q0,q1,q2'
+[^:]*:52: Error: syntax error -- `vqdmullbeq.s32 q0,q1,q2'
+[^:]*:53: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmullbt.s32 q0,q1,q2'
+[^:]*:55: Error: instruction missing MVE vector predication code -- `vqdmullb.s32 q0,q1,q2'
diff --git a/gas/testsuite/gas/arm/mve-vqdmull-bad.s b/gas/testsuite/gas/arm/mve-vqdmull-bad.s
new file mode 100644
index 0000000..fac7d5f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmull-bad.s
@@ -0,0 +1,55 @@
+.macro cond op, lastreg
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().s16 q0, q1, \lastreg
+.endr
+.endm
+
+.syntax unified
+.thumb
+vqdmullt.s8 q0, q1, q2
+vqdmullt.u8 q0, q1, q2
+vqdmullt.i16 q0, q1, q2
+vqdmullt.s64 q0, q1, q2
+vqdmullb.s8 q0, q1, q2
+vqdmullb.u8 q0, q1, q2
+vqdmullb.i16 q0, q1, q2
+vqdmullb.s64 q0, q1, q2
+vqdmullt.s8 q0, q1, r2
+vqdmullt.u8 q0, q1, r2
+vqdmullt.i16 q0, q1, r2
+vqdmullt.s64 q0, q1, r2
+vqdmullb.s8 q0, q1, r2
+vqdmullb.u8 q0, q1, r2
+vqdmullb.i16 q0, q1, r2
+vqdmullb.s64 q0, q1, r2
+vqdmullt.s32 q0, q0, q2
+vqdmullt.s32 q0, q1, q0
+vqdmullb.s32 q0, q0, q2
+vqdmullb.s32 q0, q1, q0
+vqdmullt.s32 q0, q0, r2
+vqdmullb.s32 q0, q0, r2
+vqdmullt.s16 q0, q0, sp
+vqdmullt.s16 q0, q0, pc
+vqdmullb.s16 q0, q0, sp
+vqdmullb.s16 q0, q0, pc
+cond vqdmullt, q2
+cond vqdmullb, q2
+cond vqdmullt, r2
+cond vqdmullb, r2
+it eq
+vqdmullteq.s32 q0, q1, q2
+vqdmullteq.s32 q0, q1, q2
+vpst
+vqdmullteq.s32 q0, q1, q2
+vqdmulltt.s32 q0, q1, q2
+vpst
+vqdmullt.s32 q0, q1, q2
+it eq
+vqdmullbeq.s32 q0, q1, q2
+vqdmullbeq.s32 q0, q1, q2
+vpst
+vqdmullbeq.s32 q0, q1, q2
+vqdmullbt.s32 q0, q1, q2
+vpst
+vqdmullb.s32 q0, q1, q2