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| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-04-26 14:09:34 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-04-26 14:09:34 -0600 |
| commit | 1656d3f8ef56a16745689c03269412988ebcaa54 (patch) | |
| tree | b329b8cd37a07f85f718ba3fbf1f2a0e8c2c8893 /gas/testsuite | |
| parent | dcdec68b0b5371c700bc6152de9c20eb1bdfa287 (diff) | |
| download | gdb-1656d3f8ef56a16745689c03269412988ebcaa54.zip gdb-1656d3f8ef56a16745689c03269412988ebcaa54.tar.gz gdb-1656d3f8ef56a16745689c03269412988ebcaa54.tar.bz2 | |
RISC-V: Support XVentanaCondOps extension
Ventana Micro has published the specification for their
XVentanaCondOps ("conditional ops") extension at
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
which contains two new instructions
- vt.maskc
- vt.maskcn
that can be used in constructing branchless sequences for
various conditional-arithmetic, conditional-logical, and
conditional-select operations.
To support such vendor-defined instructions in the mainline binutils,
this change also adds a riscv_supported_vendor_x_ext secondary
dispatch table (but also keeps the behaviour of allowing any unknow
X-extension to be specified in addition to the known ones from this
table).
As discussed, this change already includes the planned/agreed future
requirements for X-extensions (which are likely to be captured in the
riscv-toolchain-conventions repository):
- a public specification document is available (see above) and is
referenced from the gas-documentation
- the naming follows chapter 27 of the RISC-V ISA specification
- instructions are prefixed by a vendor-prefix (vt for Ventana)
to ensure that they neither conflict with future standard
extensions nor clash with other vendors
bfd/ChangeLog:
* elfxx-riscv.c (riscv_get_default_ext_version): Add riscv_supported_vendor_x_ext.
(riscv_multi_subset_supports): Recognize INSN_CLASS_XVENTANACONDOPS.
gas/ChangeLog:
* doc/c-riscv.texi: Add section to list custom extensions and
their documentation URLs.
* testsuite/gas/riscv/x-ventana-condops.d: New test.
* testsuite/gas/riscv/x-ventana-condops.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h Add vt.maskc and vt.maskcn.
* opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_XVENTANACONDOPS.
opcodes/ChangeLog:
* riscv-opc.c: Add vt.maskc and vt.maskcn.
Series-version: 1
Series-to: binutils@sourceware.org
Series-cc: Kito Cheng <kito.cheng@sifive.com>
Series-cc: Nelson Chu <nelson.chu@sifive.com>
Series-cc: Greg Favor <gfavor@ventanamicro.com>
Series-cc: Christoph Muellner <cmuellner@gcc.gnu.org>
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/riscv/x-ventana-condops.d | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-ventana-condops.s | 4 |
2 files changed, 16 insertions, 0 deletions
diff --git a/gas/testsuite/gas/riscv/x-ventana-condops.d b/gas/testsuite/gas/riscv/x-ventana-condops.d new file mode 100644 index 0000000..cab0cc8 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-ventana-condops.d @@ -0,0 +1,12 @@ +#as: -march=rv64i_xventanacondops1p0 +#source: x-ventana-condops.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+0:[ ]+00c5e57b[ ]+vt.maskc[ ]+a0,a1,a2 +[ ]+4:[ ]+00e6f57b[ ]+vt.maskcn[ ]+a0,a3,a4 diff --git a/gas/testsuite/gas/riscv/x-ventana-condops.s b/gas/testsuite/gas/riscv/x-ventana-condops.s new file mode 100644 index 0000000..562cf73 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-ventana-condops.s @@ -0,0 +1,4 @@ +target: + vt.maskc a0, a1, a2 + vt.maskcn a0, a3, a4 + |