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authorRichard Earnshaw <richard.earnshaw@arm.com>2011-06-09 09:59:34 +0000
committerRichard Earnshaw <richard.earnshaw@arm.com>2011-06-09 09:59:34 +0000
commitc56791bbad4c8e1e0afbf6b3ae4a5d7e91ee8742 (patch)
treeb552425a484e3496e773ac974f2609076b236d98 /gas/testsuite
parent2ddcd4af494e35b07b9fd2ccaead33f17300652a (diff)
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2011-06-09 James Greenhalgh <james.greenhalgh@arm.com>
* config/tc-arm.c (do_ldrd): Warn in unpredictable cases. 2011-06-09 James Greenhalgh <james.greenhalgh@arm.com> * gas/arm/ldrd-unpredicatble.d: New testcase. * gas/arm/ldrd-unpredicatble.s: Likewise. * gas/arm/ldrd-unpredicatble.l: Likewise.
Diffstat (limited to 'gas/testsuite')
-rw-r--r--gas/testsuite/ChangeLog6
-rw-r--r--gas/testsuite/gas/arm/ldrd-unpredictable.d2
-rw-r--r--gas/testsuite/gas/arm/ldrd-unpredictable.l7
-rw-r--r--gas/testsuite/gas/arm/ldrd-unpredictable.s14
4 files changed, 29 insertions, 0 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index f7a7079..44b8b9e 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2011-06-09 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * gas/arm/ldrd-unpredicatble.d: New testcase.
+ * gas/arm/ldrd-unpredicatble.s: Likewise.
+ * gas/arm/ldrd-unpredicatble.l: Likewise.
+
2011-06-02 Jie Zhang <jie@codesourcery.com>
Nathan Sidwell <nathan@codesourcery.com>
diff --git a/gas/testsuite/gas/arm/ldrd-unpredictable.d b/gas/testsuite/gas/arm/ldrd-unpredictable.d
new file mode 100644
index 0000000..10561b8
--- /dev/null
+++ b/gas/testsuite/gas/arm/ldrd-unpredictable.d
@@ -0,0 +1,2 @@
+# name: Unpredictable LDRD and STRD instructions. - ARM
+# error-output: ldrd-unpredictable.l
diff --git a/gas/testsuite/gas/arm/ldrd-unpredictable.l b/gas/testsuite/gas/arm/ldrd-unpredictable.l
new file mode 100644
index 0000000..3271714
--- /dev/null
+++ b/gas/testsuite/gas/arm/ldrd-unpredictable.l
@@ -0,0 +1,7 @@
+[^:]*: Assembler messages:
+[^:]*:6: Warning: index register overlaps transfer register
+[^:]*:7: Warning: index register overlaps transfer register
+[^:]*:8: Warning: source register same as write-back base
+[^:]*:9: Warning: base register written back, and overlaps second transfer register
+[^:]*:13: Warning: source register same as write-back base
+[^:]*:14: Warning: base register written back, and overlaps second transfer register
diff --git a/gas/testsuite/gas/arm/ldrd-unpredictable.s b/gas/testsuite/gas/arm/ldrd-unpredictable.s
new file mode 100644
index 0000000..9bc2075
--- /dev/null
+++ b/gas/testsuite/gas/arm/ldrd-unpredictable.s
@@ -0,0 +1,14 @@
+.syntax unified
+
+.arm
+
+@ LDRD
+ldrd r0,r1,[r0,r1] @ unpredictable
+ldrd r0,r1,[r1,r0] @ ditto
+ldrd r0,r1,[r0,r2]! @ ditto
+ldrd r0,r1,[r1,r2]! @ ditto
+
+@ STRD
+
+strd r0,r1,[r0,r2]! @ ditto
+strd r0,r1,[r1,r2]! @ ditto