[binutils, Arm] Add support for conditional instructions in Armv8.1-M Mainline

This patch adds the following instructions which are part of the
Armv8.1-M Mainline:
CINC
CINV
CNEG
CSINC
CSINV
CSNEG
CSET
CSETM
CSEL

gas/ChangeLog:

2019-05-21  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-arm.c (TOGGLE_BIT): New.
	(T16_32_TAB): New entries for cinc, cinv, cneg, csinc,
	csinv, csneg, cset, csetm and csel.
	(operand_parse_code): New OP_RR_ZR.
	(parse_operand): Handle case for OP_RR_ZR.
	(do_t_cond): New.
	(insns): New instructions for cinc, cinv, cneg, csinc,
	csinv, csneg, cset, csetm, csel.
	* testsuite/gas/arm/armv8_1-m-cond-bad.d: New test.
	* testsuite/gas/arm/armv8_1-m-cond-bad.l: New test.
	* testsuite/gas/arm/armv8_1-m-cond-bad.s: New test.
	* testsuite/gas/arm/armv8_1-m-cond.d: New test.
	* testsuite/gas/arm/armv8_1-m-cond.s: New test.

opcodes/ChangeLog:

2019-05-21  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (enum mve_instructions): New enum
	for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
	and cneg.
	(mve_opcodes): New instructions as above.
	(is_mve_encoding_conflict): Add cases for csinc, csinv,
	csneg and csel.
	(print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.

5 files changed, 65 insertions, 0 deletions

diff --git a/gas/testsuite/gas/arm/armv8_1-m-cond-bad.d b/gas/testsuite/gas/arm/armv8_1-m-cond-bad.d
new file mode 100644
index 0000000..d953f9a
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-cond-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid Armv8.1-M Mainline conditional instructions
+#source: armv8_1-m-cond-bad.s
+#as: -march=armv8.1-m.main
+#error_output: armv8_1-m-cond-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_1-m-cond-bad.l b/gas/testsuite/gas/arm/armv8_1-m-cond-bad.l
new file mode 100644
index 0000000..47eafcf
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-cond-bad.l
@@ -0,0 +1,8 @@
+.*: Assembler messages:
+.*: Error: condition required -- `cset r4,r2,ne'
+.*: Error: r13 not allowed here -- `csetm sp,ne'
+.*: Error: r15 not allowed here -- `cinc r3,pc,lt'
+.*: Error: r15 not allowed here -- `cinv pc,r2,lt'
+.*: Error: r13 not allowed here -- `cneg r3,sp,lt'
+.*: Error: instruction not allowed in IT block -- `csinc r3,r2,r4,lt'
+.*: Error: instruction cannot be conditional -- `csnegne r3,r2,r4,lt'
diff --git a/gas/testsuite/gas/arm/armv8_1-m-cond-bad.s b/gas/testsuite/gas/arm/armv8_1-m-cond-bad.s
new file mode 100644
index 0000000..a7d98ed
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-cond-bad.s
@@ -0,0 +1,15 @@
+        .syntax unified
+        .text
+
+foo:
+	cset	r4, r2, ne
+	csetm	sp, ne
+	cinc	r3, pc, lt
+	cinv	pc, r2, lt
+	cneg	r3, sp, lt
+	it eq
+	csinc	r3, r2, r4, lt
+	csinv	r3, r4, r4, lt
+	it ne
+	csnegne	r3, r2, r4, lt
+	csinv	r3, r4, r4, lt
diff --git a/gas/testsuite/gas/arm/armv8_1-m-cond.d b/gas/testsuite/gas/arm/armv8_1-m-cond.d
new file mode 100644
index 0000000..171da37
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-cond.d
@@ -0,0 +1,21 @@
+#name: Valid Armv8.1-M Mainline conditional instructions
+#source: armv8_1-m-cond.s
+#as: -march=armv8.1-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> ea5f 940f 	cset	r4, ne
+0[0-9a-f]+ <[^>]+> ea5f a40f 	csetm	r4, ne
+0[0-9a-f]+ <[^>]+> ea52 93a2 	cinc	r3, r2, lt
+0[0-9a-f]+ <[^>]+> ea52 a3a2 	cinv	r3, r2, lt
+0[0-9a-f]+ <[^>]+> ea52 b3a2 	cneg	r3, r2, lt
+0[0-9a-f]+ <[^>]+> ea52 93b4 	csinc	r3, r2, r4, lt
+0[0-9a-f]+ <[^>]+> ea54 93b4 	cinc	r3, r4, ge
+0[0-9a-f]+ <[^>]+> ea5f 93bf 	cset	r3, ge
+0[0-9a-f]+ <[^>]+> ea52 a3b4 	csinv	r3, r2, r4, lt
+0[0-9a-f]+ <[^>]+> ea54 a3b4 	cinv	r3, r4, ge
+0[0-9a-f]+ <[^>]+> ea5f a3bf 	csetm	r3, ge
+0[0-9a-f]+ <[^>]+> ea52 b3b4 	csneg	r3, r2, r4, lt
+0[0-9a-f]+ <[^>]+> ea54 b3b4 	cneg	r3, r4, ge
diff --git a/gas/testsuite/gas/arm/armv8_1-m-cond.s b/gas/testsuite/gas/arm/armv8_1-m-cond.s
new file mode 100644
index 0000000..f192d5f
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-cond.s
@@ -0,0 +1,17 @@
+        .syntax unified
+        .text
+
+foo:
+	cset	r4, ne
+	csetm	r4, ne
+	cinc	r3, r2, lt
+	cinv	r3, r2, lt
+	cneg	r3, r2, lt
+	csinc	r3, r2, r4, lt
+	csinc	r3, r4, r4, lt
+	csinc	r3, zr, zr, lt
+	csinv	r3, r2, r4, lt
+	csinv	r3, r4, r4, lt
+	csinv	r3, zr, zr, lt
+	csneg	r3, r2, r4, lt
+	csneg	r3, r4, r4, lt