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| author | Jim Wilson <jimw@sifive.com> | 2018-08-31 12:23:05 -0700 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2018-08-31 12:23:05 -0700 |
| commit | be192bc284b329fa0b38646bd3df9a02b880a704 (patch) | |
| tree | 3b58a1801539c3e736f2e8b7dc27f87590e9cbff /gas/testsuite | |
| parent | c8c81635739435a31860ff5f1e49743d80321f43 (diff) | |
| download | gdb-be192bc284b329fa0b38646bd3df9a02b880a704.zip gdb-be192bc284b329fa0b38646bd3df9a02b880a704.tar.gz gdb-be192bc284b329fa0b38646bd3df9a02b880a704.tar.bz2 | |
RISC-V: Correct the requirement of compressed floating point instructions
2018-08-31 Kito Cheng <kito@andestech.com>
gas/
* testsuite/gas/riscv/c-fld-fsd-fail.d: New.
* testsuite/gas/riscv/c-fld-fsd-fail.l: Likewise.
* testsuite/gas/riscv/c-fld-fsd-fail.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
compressed floating point instructions.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/riscv/c-fld-fsd-fail.d | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/c-fld-fsd-fail.l | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/c-fld-fsd-fail.s | 3 |
3 files changed, 9 insertions, 0 deletions
diff --git a/gas/testsuite/gas/riscv/c-fld-fsd-fail.d b/gas/testsuite/gas/riscv/c-fld-fsd-fail.d new file mode 100644 index 0000000..a90f7b4f --- /dev/null +++ b/gas/testsuite/gas/riscv/c-fld-fsd-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ic +#source: c-fld-fsd-fail.s +#error-output: c-fld-fsd-fail.l diff --git a/gas/testsuite/gas/riscv/c-fld-fsd-fail.l b/gas/testsuite/gas/riscv/c-fld-fsd-fail.l new file mode 100644 index 0000000..7d99abb --- /dev/null +++ b/gas/testsuite/gas/riscv/c-fld-fsd-fail.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: unrecognized opcode `fld fa0,0\(a0\)' +.*: Error: unrecognized opcode `fsd fa0,0\(a0\)' diff --git a/gas/testsuite/gas/riscv/c-fld-fsd-fail.s b/gas/testsuite/gas/riscv/c-fld-fsd-fail.s new file mode 100644 index 0000000..1cb0c5e --- /dev/null +++ b/gas/testsuite/gas/riscv/c-fld-fsd-fail.s @@ -0,0 +1,3 @@ +target: + fld fa0, 0(a0) + fsd fa0, 0(a0) |