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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-05-16 12:07:22 +0100 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-05-16 16:36:50 +0100 |
| commit | a710b305c5ca8307e8b9d14bbb014641f60d3b48 (patch) | |
| tree | aacf17fec9826dc841af416f99d955de240cda69 /gas/testsuite | |
| parent | 4aa88b50c4eec0256bcba33e02135f224a725d68 (diff) | |
| download | gdb-a710b305c5ca8307e8b9d14bbb014641f60d3b48.zip gdb-a710b305c5ca8307e8b9d14bbb014641f60d3b48.tar.gz gdb-a710b305c5ca8307e8b9d14bbb014641f60d3b48.tar.bz2 | |
[PATCH 32/57][Arm][GAS] Add support for MVE instructions: vrintn, vrintx, vrinta, vrintz, vrintm and vrintp
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_vrint_1): Accept MVE variants.
(insns): Change entries to accept MVE variants.
* testsuite/gas/arm/mve-vrint-bad.d: New test.
* testsuite/gas/arm/mve-vrint-bad.l: New test.
* testsuite/gas/arm/mve-vrint-bad.s: New test.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/arm/mve-vrint-bad.d | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/mve-vrint-bad.l | 80 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/mve-vrint-bad.s | 25 |
3 files changed, 110 insertions, 0 deletions
diff --git a/gas/testsuite/gas/arm/mve-vrint-bad.d b/gas/testsuite/gas/arm/mve-vrint-bad.d new file mode 100644 index 0000000..081a008 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vrint-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VRINT instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vrint-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vrint-bad.l b/gas/testsuite/gas/arm/mve-vrint-bad.l new file mode 100644 index 0000000..1d68a82 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vrint-bad.l @@ -0,0 +1,80 @@ +[^:]*: Assembler messages: +[^:]*:13: Error: bad type in SIMD instruction -- `vrintn.i16 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintn.f64 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintx.i16 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintx.f64 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrinta.i16 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrinta.f64 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintz.i16 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintz.f64 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintm.i16 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintm.f64 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintp.i16 q0,q1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrintp.f64 q0,q1' +[^:]*:14: Error: invalid rounding mode -- `vrintr.f16 q0,q1' +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Error: syntax error -- `vrintneq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintneq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintneq.f16 q0,q1' +[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintnt.f16 q0,q1' +[^:]*:25: Error: instruction missing MVE vector predication code -- `vrintn.f16 q0,q1' +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Error: syntax error -- `vrintxeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintxeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintxeq.f16 q0,q1' +[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintxt.f16 q0,q1' +[^:]*:25: Error: instruction missing MVE vector predication code -- `vrintx.f16 q0,q1' +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Error: syntax error -- `vrintaeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintaeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintaeq.f16 q0,q1' +[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintat.f16 q0,q1' +[^:]*:25: Error: instruction missing MVE vector predication code -- `vrinta.f16 q0,q1' +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Error: syntax error -- `vrintzeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintzeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintzeq.f16 q0,q1' +[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintzt.f16 q0,q1' +[^:]*:25: Error: instruction missing MVE vector predication code -- `vrintz.f16 q0,q1' +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Error: syntax error -- `vrintmeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintmeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintmeq.f16 q0,q1' +[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintmt.f16 q0,q1' +[^:]*:25: Error: instruction missing MVE vector predication code -- `vrintm.f16 q0,q1' +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Error: syntax error -- `vrintpeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintpeq.f16 q0,q1' +[^:]*:25: Error: syntax error -- `vrintpeq.f16 q0,q1' +[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vrintpt.f16 q0,q1' +[^:]*:25: Error: instruction missing MVE vector predication code -- `vrintp.f16 q0,q1' diff --git a/gas/testsuite/gas/arm/mve-vrint-bad.s b/gas/testsuite/gas/arm/mve-vrint-bad.s new file mode 100644 index 0000000..7e9a531 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vrint-bad.s @@ -0,0 +1,25 @@ +.macro cond, mode +.irp cond, eq, ne, gt, ge, lt, le +it \cond +vrint\mode\().f16 q0, q1 +.endr +.endm + +.syntax unified +.thumb +.irp mode, n, x, a, z, m, p +vrint\mode\().i16 q0, q1 +vrint\mode\().f64 q0, q1 +.endr +vrintr.f16 q0, q1 +.irp mode, n, x, a, z, m, p +cond \mode +it eq +vrint\mode\()eq.f16 q0, q1 +vrint\mode\()eq.f16 q0, q1 +vpst +vrint\mode\()eq.f16 q0, q1 +vrint\mode\()t.f16 q0, q1 +vpst +vrint\mode\().f16 q0, q1 +.endr |