[PATCH 18/57][Arm][GAS] Add support for MVE instructions: vhcadd, vhadd, vhsub and vrhadd

gas/ChangeLog:
2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (enum operand_parse_code): New operand.
	(parse_operands): Handle new operand.
	(mve_encode_qqr): Change to support new instructions.
	(enum vfp_or_neon_is_neon_bits): Moved.
	(vfp_or_neon_is_neon): Moved.
	(check_simd_pred_availability): Moved.
	(do_neon_dyadic_i_su): Changed to support MVE variants.
	(neon_dyadic_misc): Changed mve_encode_qqr call.
	(do_mve_vbrsr): Likewise.
	(do_mve_vhcadd): New encoding function.
	(insns): Change existing to accept MVE variants and add new.
	* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.d: New test.
	* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.l: New test.
	* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.s: New test.
	* testsuite/gas/arm/mve-vhcadd-bad.d: New test.
	* testsuite/gas/arm/mve-vhcadd-bad.l: New test.
	* testsuite/gas/arm/mve-vhcadd-bad.s: New test.

6 files changed, 190 insertions, 0 deletions

diff --git a/gas/testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.d b/gas/testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.d
new file mode 100644
index 0000000..acb12a4
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VHADD, VHSUB and VRHADD instructions
+#as: -march=armv8.1-m.main+mve
+#error_output: mve-vhadd-vhsub-vrhadd-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.l b/gas/testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.l
new file mode 100644
index 0000000..e49015c
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.l
@@ -0,0 +1,71 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vhadd.i8 q0,q1,q2'
+[^:]*:11: Error: bad type in SIMD instruction -- `vhadd.s64 q0,q1,q2'
+[^:]*:12: Error: bad type in SIMD instruction -- `vhadd.i8 q0,q1,r2'
+[^:]*:13: Error: bad type in SIMD instruction -- `vhadd.s64 q0,q1,r2'
+[^:]*:14: Error: bad type in SIMD instruction -- `vhsub.i16 q0,q1,q2'
+[^:]*:15: Error: bad type in SIMD instruction -- `vhsub.u64 q0,q1,q2'
+[^:]*:16: Error: bad type in SIMD instruction -- `vhsub.i16 q0,q1,r2'
+[^:]*:17: Error: bad type in SIMD instruction -- `vhsub.u64 q0,q1,r2'
+[^:]*:18: Error: bad type in SIMD instruction -- `vrhadd.i32 q0,q1,q2'
+[^:]*:19: Error: bad type in SIMD instruction -- `vrhadd.s64 q0,q1,q2'
+[^:]*:20: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:21: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:22: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:23: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:24: Error: garbage following instruction -- `vrhadd.s8 q0,q1,r2'
+[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:31: Error: syntax error -- `vhaddeq.s8 q0,q1,r2'
+[^:]*:32: Error: syntax error -- `vhaddeq.s8 q0,q1,r2'
+[^:]*:34: Error: syntax error -- `vhaddeq.s8 q0,q1,r2'
+[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vhaddt.s8 q0,q1,r2'
+[^:]*:37: Error: instruction missing MVE vector predication code -- `vhadd.s8 q0,q1,r2'
+[^:]*:39: Error: syntax error -- `vhaddeq.s8 q0,q1,q2'
+[^:]*:40: Error: syntax error -- `vhaddeq.s8 q0,q1,q2'
+[^:]*:42: Error: syntax error -- `vhaddeq.s8 q0,q1,q2'
+[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vhaddt.s8 q0,q1,q2'
+[^:]*:45: Error: instruction missing MVE vector predication code -- `vhadd.s8 q0,q1,q2'
+[^:]*:47: Error: syntax error -- `vhsubeq.s8 q0,q1,r2'
+[^:]*:48: Error: syntax error -- `vhsubeq.s8 q0,q1,r2'
+[^:]*:50: Error: syntax error -- `vhsubeq.s8 q0,q1,r2'
+[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vhsubt.s8 q0,q1,r2'
+[^:]*:53: Error: instruction missing MVE vector predication code -- `vhsub.s8 q0,q1,r2'
+[^:]*:55: Error: syntax error -- `vhsubeq.s8 q0,q1,q2'
+[^:]*:56: Error: syntax error -- `vhsubeq.s8 q0,q1,q2'
+[^:]*:58: Error: syntax error -- `vhsubeq.s8 q0,q1,q2'
+[^:]*:59: Error: vector predicated instruction should be in VPT/VPST block -- `vhsubt.s8 q0,q1,q2'
+[^:]*:61: Error: instruction missing MVE vector predication code -- `vhsub.s8 q0,q1,q2'
+[^:]*:63: Error: syntax error -- `vrhaddeq.s8 q0,q1,q2'
+[^:]*:64: Error: syntax error -- `vrhaddeq.s8 q0,q1,q2'
+[^:]*:66: Error: syntax error -- `vrhaddeq.s8 q0,q1,q2'
+[^:]*:67: Error: vector predicated instruction should be in VPT/VPST block -- `vrhaddt.s8 q0,q1,q2'
+[^:]*:69: Error: instruction missing MVE vector predication code -- `vrhadd.s8 q0,q1,q2'
diff --git a/gas/testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.s b/gas/testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.s
new file mode 100644
index 0000000..bebefc9
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.s
@@ -0,0 +1,69 @@
+.macro cond, op, lastreg
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().s8 q0, q1, \lastreg
+.endr
+.endm
+
+.syntax unified
+.thumb
+vhadd.i8 q0, q1, q2
+vhadd.s64 q0, q1, q2
+vhadd.i8 q0, q1, r2
+vhadd.s64 q0, q1, r2
+vhsub.i16 q0, q1, q2
+vhsub.u64 q0, q1, q2
+vhsub.i16 q0, q1, r2
+vhsub.u64 q0, q1, r2
+vrhadd.i32 q0, q1, q2
+vrhadd.s64 q0, q1, q2
+vhadd.s8 q0, q1, sp
+vhadd.s8 q0, q1, pc
+vhsub.s8 q0, q1, sp
+vhsub.s8 q0, q1, pc
+vrhadd.s8 q0, q1, r2
+cond vhadd, r2
+cond vhadd, q2
+cond vhsub, r2
+cond vhsub, q2
+cond vrhadd, q2
+it eq
+vhaddeq.s8 q0, q1, r2
+vhaddeq.s8 q0, q1, r2
+vpst
+vhaddeq.s8 q0, q1, r2
+vhaddt.s8 q0, q1, r2
+vpst
+vhadd.s8 q0, q1, r2
+it eq
+vhaddeq.s8 q0, q1, q2
+vhaddeq.s8 q0, q1, q2
+vpst
+vhaddeq.s8 q0, q1, q2
+vhaddt.s8 q0, q1, q2
+vpst
+vhadd.s8 q0, q1, q2
+it eq
+vhsubeq.s8 q0, q1, r2
+vhsubeq.s8 q0, q1, r2
+vpst
+vhsubeq.s8 q0, q1, r2
+vhsubt.s8 q0, q1, r2
+vpst
+vhsub.s8 q0, q1, r2
+it eq
+vhsubeq.s8 q0, q1, q2
+vhsubeq.s8 q0, q1, q2
+vpst
+vhsubeq.s8 q0, q1, q2
+vhsubt.s8 q0, q1, q2
+vpst
+vhsub.s8 q0, q1, q2
+it eq
+vrhaddeq.s8 q0, q1, q2
+vrhaddeq.s8 q0, q1, q2
+vpst
+vrhaddeq.s8 q0, q1, q2
+vrhaddt.s8 q0, q1, q2
+vpst
+vrhadd.s8 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/mve-vhcadd-bad.d b/gas/testsuite/gas/arm/mve-vhcadd-bad.d
new file mode 100644
index 0000000..51b37a4
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vhcadd-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VHCADD instructions
+#as: -march=armv8.1-m.main+mve
+#error_output: mve-vhcadd-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vhcadd-bad.l b/gas/testsuite/gas/arm/mve-vhcadd-bad.l
new file mode 100644
index 0000000..6120072
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vhcadd-bad.l
@@ -0,0 +1,17 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vhcadd.u8 q0,q1,q2,#90'
+[^:]*:11: Error: bad type in SIMD instruction -- `vhcadd.i8 q0,q1,q2,#90'
+[^:]*:12: Error: bad type in SIMD instruction -- `vhcadd.s64 q0,q1,q2,#90'
+[^:]*:13: Error: immediate out of range -- `vhcadd.s8 q0,q1,q2,#0'
+[^:]*:14: Error: immediate out of range -- `vhcadd.s8 q0,q1,q2,#180'
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Error: syntax error -- `vhcaddeq.s8 q0,q1,q2,#90'
+[^:]*:18: Error: syntax error -- `vhcaddeq.s8 q0,q1,q2,#90'
+[^:]*:20: Error: syntax error -- `vhcaddeq.s8 q0,q1,q2,#90'
+[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vhcaddt.s8 q0,q1,q2,#90'
+[^:]*:23: Error: instruction missing MVE vector predication code -- `vhcadd.s8 q0,q1,q2,#90'
diff --git a/gas/testsuite/gas/arm/mve-vhcadd-bad.s b/gas/testsuite/gas/arm/mve-vhcadd-bad.s
new file mode 100644
index 0000000..ede5b7e
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vhcadd-bad.s
@@ -0,0 +1,23 @@
+.macro cond
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vhcadd.s8 q0, q1, q2, #90
+.endr
+.endm
+
+.syntax unified
+.thumb
+vhcadd.u8 q0, q1, q2, #90
+vhcadd.i8 q0, q1, q2, #90
+vhcadd.s64 q0, q1, q2, #90
+vhcadd.s8 q0, q1, q2, #0
+vhcadd.s8 q0, q1, q2, #180
+cond
+it eq
+vhcaddeq.s8 q0, q1, q2, #90
+vhcaddeq.s8 q0, q1, q2, #90
+vpst
+vhcaddeq.s8 q0, q1, q2, #90
+vhcaddt.s8 q0, q1, q2, #90
+vpst
+vhcadd.s8 q0, q1, q2, #90