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author | H.J. Lu <hjl.tools@gmail.com> | 2018-08-11 14:37:14 -0700 |
---|---|---|
committer | H.J. Lu <hjl.tools@gmail.com> | 2018-08-11 14:37:32 -0700 |
commit | d871f3f48388d57721d8077e281041ed16a745cf (patch) | |
tree | 31db918f0c563c84b09de4674bb4af3548b1483c /gas/doc | |
parent | ab9e342807d132182892de1be1a92d6e91a5c1da (diff) | |
download | gdb-d871f3f48388d57721d8077e281041ed16a745cf.zip gdb-d871f3f48388d57721d8077e281041ed16a745cf.tar.gz gdb-d871f3f48388d57721d8077e281041ed16a745cf.tar.bz2 |
x86: Add CpuCMOV and CpuFXSR
There are separate CPUID feature bits for fxsave/fxrstor and cmovCC
instructions. This patch adds CpuCMOV and CpuFXSR to replace Cpu686
on corresponding instructions.
gas/
* config/tc-i386.c (cpu_arch): Add .cmov and .fxsr.
(cpu_noarch): Add nocmov and nofxsr.
* doc/c-i386.texi: Document cmov and fxsr.
opcodes/
* i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
(cpu_flags): Add CpuCMOV and CpuFXSR.
* i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
Diffstat (limited to 'gas/doc')
-rw-r--r-- | gas/doc/c-i386.texi | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index c3fce9e..c9eb178 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -141,6 +141,10 @@ accept various extension mnemonics. For example, @code{no287}, @code{no387}, @code{no687}, +@code{cmov}, +@code{nocmov}, +@code{fxsr}, +@code{nofxsr}, @code{mmx}, @code{nommx}, @code{sse}, @@ -1256,12 +1260,13 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4} @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2} -@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu} +@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu} @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8} @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3} @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1} -@item @samp{btver2} @samp{generic32} @tab @samp{generic64} -@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} +@item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64} +@item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx} +@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept} @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt} |