2000-07-31 Jason Eckhardt <jle@cygnus.com>

        * doc/c-i860.texi: New file.
        * doc/Makefile.am (CPU_DOCS): Add c-i860.texi.
        * doc/Makefile.in: Regenerate.
        * doc/all.texi: Add I860 as relevant architecture.
        * doc/as.texinfo: Include i860 dependent file c-i860.texi.

5 files changed, 100 insertions, 0 deletions

diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am
index 7352724..ac10774 100644
--- a/gas/doc/Makefile.am
+++ b/gas/doc/Makefile.am
@@ -24,6 +24,7 @@ CPU_DOCS = \
 	c-hppa.texi \
 	c-i370.texi \
 	c-i386.texi \
+	c-i860.texi \
 	c-i960.texi \
 	c-m32r.texi \
 	c-m68hc11.texi \
diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in
index ce79b5a..4e7389c 100644
--- a/gas/doc/Makefile.in
+++ b/gas/doc/Makefile.in
@@ -128,6 +128,7 @@ CPU_DOCS = \
 	c-hppa.texi \
 	c-i370.texi \
 	c-i386.texi \
+	c-i860.texi \
 	c-i960.texi \
 	c-m32r.texi \
 	c-m68hc11.texi \
diff --git a/gas/doc/all.texi b/gas/doc/all.texi
index e695067..22742b4 100644
--- a/gas/doc/all.texi
+++ b/gas/doc/all.texi
@@ -35,6 +35,7 @@
 @set HPPA
 @set I370
 @set I80386
+@set I860
 @set I960
 @set M32R
 @set M68HC11
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index c860222..8ff7577 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -5027,6 +5027,9 @@ subject, see the hardware manufacturer's manual.
 @ifset I80386
 * i386-Dependent::              Intel 80386 Dependent Features
 @end ifset
+@ifset I860
+* i860-Dependent::              Intel 80860 Dependent Features
+@end ifset
 @ifset I960
 * i960-Dependent::              Intel 80960 Dependent Features
 @end ifset
@@ -5208,6 +5211,10 @@ family.
 @include c-i386.texi
 @end ifset
 
+@ifset I860
+@include c-i860.texi
+@end ifset
+
 @ifset I960
 @include c-i960.texi
 @end ifset
diff --git a/gas/doc/c-i860.texi b/gas/doc/c-i860.texi
new file mode 100644
index 0000000..d3b989f
--- /dev/null
+++ b/gas/doc/c-i860.texi
@@ -0,0 +1,90 @@
+@c Copyright (C) 2000 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@ifset GENERIC
+@page
+@node i860-Dependent
+@chapter Intel i860 Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter Intel i860 Dependent Features
+@end ifclear
+
+@ignore
+@c FIXME: This is basically a stub for i860. There is tons more information
+that I will add later (jle@cygnus.com). The assembler is still being
+written. The i860 assembler that existed previously was never finished
+and doesn't even build. Further, its not BFD_ASSEMBLER and it doesn't
+do ELF (it doesn't do anything, but you get the point).
+@end ignore
+
+@cindex i860 support
+@menu
+* Options-i860::                i860 Command-line Options
+* Directives-i860::             i860 Machine Directives
+* Opcodes for i860::            i860 Opcodes
+@end menu
+
+@node Options-i860
+
+@section i860 Command-line Options
+@subsection SVR4 compatibility options 
+@table @code
+@item -V
+Print assembler version.
+@item -Qy
+Ignored.
+@item -Qn
+Ignored.
+@end table
+@subsection Other options 
+@table @code
+@item -EL
+Select little endian output (this is the default).
+@item -EB
+Select big endian output. Note that the i860 always reads instructions
+as little endian data, so this option only effects data and not
+instructions.
+@end table
+
+@node Directives-i860
+@section i860 Machine Directives
+
+@cindex machine directives, i860
+@cindex i860 machine directives
+
+@table @code
+@cindex @code{dual} directive, i860
+@item .dual
+Enter dual instruction mode. While this directive is supported, the
+preferred way to use dual instruction mode is to explicitly code
+the dual bit with the @code{d.} prefix.
+@end table
+
+@table @code
+@cindex @code{enddual} directive, i860
+@item .enddual
+Exit dual instruction mode. While this directive is supported, the
+preferred way to use dual instruction mode is to explicitly code
+the dual bit with the @code{d.} prefix.
+@end table
+
+@table @code
+@cindex @code{atmp} directive, i860
+@item .atmp
+Change the temporary register used when expanding pseudo operations. The
+default register is @code{r31}.
+@end table
+
+@node Opcodes for i860
+@section i860 Opcodes
+
+@cindex opcodes, i860
+@cindex i860 opcodes
+All of the Intel i860 machine instructions are supported.
+
+Some opcodes are processed beyond simply emitting a single corresponding
+instruction. For example, @samp{mov} and other instructions with larg
+displacements may be expanded into 2 or 3 instructions (FIXME: add details).
+