[gas/ChangeLog]

	* config/tc-ppc.c (md_parse_option): New -m7410, -m7450 and -m7455
	flags, equivalent to -m7400.  New -maltivec to enable AltiVec
	instructions.  New -mbook64 and -mbooke/-mbooke32 flags to enable
	64-bit and 32-bit BookE support, respectively.  Change -m403 and
	-m405 to set PPC403 option.
	(md_show_usage): Adjust for new options.
	* doc/all.texi: Set PPC.
	* doc/as.texinfo: Add PPC support and pull in c-ppc.texi.
	* doc/c-ppc.texi: New file.
	* doc/Makefile.am (CPU_DOCS): Add c-ppc.texi.
	* doc/Makefile.in: Regenerate.

[gas/testsuite/ChangeLog]
	* gas/ppc/booke.s: New test for Motorola BookE.
	* gas/ppc/booke.d: New file.
	* gas/ppc/ppc.exp: Test booke.s.

[include/opcode/ChangeLog]
	* ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_403): New opcode flags for
	BookE and PowerPC403 instructions.

[opcodes/ChangeLog]
	* ppc-opc.c (insert_de, extract_de, insert_des, extract_des): New
	instruction field instruction/extraction functions for new BookE
	DE form instructions.
	(CT): New macro for CT field in an X form instruction.
	(DE, DES, DEO, DE_MASK): New macros for DE/DES fields in DE form
	instructions.
	(PPC64): Don't include PPC_OPCODE_PPC.
	(403): New opcode macro for PPC403 processors.
	(BOOKE): New opcode macro for BookE processors.
	(bce, bcel, bcea, bcela, bclre, bclrel: New BookE instructions.
	(bcctre, bcctrel, be, bel, bea, bela, icbt, icbte, lwzxe): Likewise.
	(dcbste, lwzuxe, luxe, dcbfe, lbzxe, lwarxe, lbzuxe): Likewise.
	(stwcxe, stwxe, stxe, stwuxe, stuxe, stbxe, dcbtste, stbuxe): Likewise.
	(mfapidi, dcbte, lhzxe, lhzuxe, lhaxe, lhauxe, subfe64): Likewise.
	(subfeo64, adde64, addeo64, sthxe, sthuxe, subfze64): Likewise.
	(subfzeo64, addze64, addzeo64, dcbie, subfme64, subfmeo64): Likewise.
	(addme64, addmeo64, stdcxe., mcrxr64, lwbrxe, lfsxe, lfsuxe): Likewise.
	(lfdxe, lfduxe, stwbrxe, stfsxe, stfsuxe, stfdxe, dcbae): Likewise.
	(stfduxe, tlbivax, tlbivaxe, lhbrxe, ldxe, lduxe, tlbsx): Likewise.
	(tlbsxe, sthbrxe, stdxe, stduxe, icbie, stfiwxe, dcbze, lbze): Likewise.
	(lbzue, ldue, lhze, lhzue, lhae, lhaue, lwze, lwzue): Likewise.
	(stbe, stbue, sthe, sthue, stwe, stwue, lfse, lfsue, lfde): Likewise.
	(lfdue, stde, stdue, stfse, stfsue, stfde, stfdue): Likewise.

	* ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): Look
	for a disassembler option of `booke', `booke32' or `booke64' to enable
	BookE support in the disassembler.

5 files changed, 119 insertions, 0 deletions

diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am
index abf95d4..d20c3c0 100644
--- a/gas/doc/Makefile.am
+++ b/gas/doc/Makefile.am
@@ -42,6 +42,7 @@ CPU_DOCS = \
 	c-ns32k.texi \
 	c-pdp11.texi \
 	c-pj.texi \
+	c-ppc.texi \
 	c-sh.texi \
 	c-sparc.texi \
         c-tic54x.texi \
diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in
index 241d3b2..f36b2a0 100644
--- a/gas/doc/Makefile.in
+++ b/gas/doc/Makefile.in
@@ -152,6 +152,7 @@ CPU_DOCS = \
 	c-ns32k.texi \
 	c-pdp11.texi \
 	c-pj.texi \
+	c-ppc.texi \
 	c-sh.texi \
 	c-sparc.texi \
         c-tic54x.texi \
diff --git a/gas/doc/all.texi b/gas/doc/all.texi
index f2465c2..6ba731b 100644
--- a/gas/doc/all.texi
+++ b/gas/doc/all.texi
@@ -46,6 +46,7 @@
 @set MIPS
 @set PDP11
 @set PJ
+@set PPC
 @set SH
 @set SPARC
 @set C54X
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index 83f1435..e4a0fc1 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -45,6 +45,7 @@
 @set MIPS
 @set PDP11
 @set PJ
+@set PPC
 @set SH
 @set SPARC
 @set C54X
@@ -291,6 +292,16 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
 @ifset PJ
  [ -mb | -me ]
 @end ifset
+@ifset PPC
+ [ -mpwrx | -mpwr2 | -mpwr | -m601 | -mppc | -mppc32 | -m603 | -m604 |
+   -m403 | -m405 | -mppc64 | -m620 | -mppc64bridge | -mbooke |
+   -mbooke32 | -mbooke64 ]
+ [ -mcom | -many | -maltivec ] [ -memb ]
+ [ -mregnames | -mno-regnames ]
+ [ -mrelocatable | -mrelocatable-lib ]
+ [ -mlittle | -mlittle-endian | -mbig, -mbig-endian ]
+ [ -msolaris | -mno-solaris ]
+@end ifset
 @ifset SPARC
 @c The order here is important.  See c-sparc.texi.
  [ -Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite
@@ -1846,6 +1857,9 @@ is considered a comment and is ignored.  The line comment character is
 @ifset PJ
 @samp{;} for picoJava;
 @end ifset
+@ifset PPC
+@samp{;} for Motorola PowerPC;
+@end ifset
 @ifset SH
 @samp{!} for the Hitachi SH;
 @end ifset
@@ -5560,6 +5574,9 @@ subject, see the hardware manufacturer's manual.
 @ifset PJ
 * PJ-Dependent::                picoJava Dependent Features
 @end ifset
+@ifset PPC
+* PPC-Dependent::               PowerPC Dependent Features
+@end ifset
 @ifset SPARC
 * Sparc-Dependent::             SPARC Dependent Features
 @end ifset
@@ -5687,6 +5704,10 @@ family.
 @include c-pj.texi
 @end ifset
 
+@ifset PPC
+@include c-ppc.texi
+@end ifset
+
 @ifset SH
 @include c-sh.texi
 @end ifset
diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi
new file mode 100644
index 0000000..cae9e23
--- /dev/null
+++ b/gas/doc/c-ppc.texi
@@ -0,0 +1,95 @@
+@c Copyright 2001
+@c Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@ifset GENERIC
+@page
+@node PPC-Dependent
+@chapter PowerPC Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter PowerPC Dependent Features
+@end ifclear
+
+@cindex PowerPC support
+@menu
+* PowerPC-Opts::                Options
+@end menu
+
+@node PowerPC-Opts
+@section Options
+
+@cindex options for PowerPC
+@cindex PowerPC options
+@cindex architectures, PowerPC
+@cindex PowerPC architectures
+The PowerPC chip family includes several successive levels, using the same
+core instruction set, but including a few additional instructions at
+each level.  There are exceptions to this however.  For details on what
+instructions each variant supports, please see the chip's architecture
+reference manual.
+
+The following table lists all available PowerPC options.
+
+@table @code
+@item -mpwrx | -mpwr2
+Generate code for IBM POWER/2 (RIOS2).
+
+@item -mpwr
+Generate code for IBM POWER (RIOS1)
+
+@item -m601
+Generate code for Motorola PowerPC 601.
+
+@item -mppc, -mppc32, -m603, -m604
+Generate code for Motorola PowerPC 603/604.
+
+@item -m403, -m405
+Generate code for Motorola PowerPC 403/405.
+
+@item -mppc64, -m620
+Generate code for Motorola PowerPC 620.
+
+@item -mppc64bridge
+Generate code for PowerPC 64, including bridge insns.
+
+@item -mbooke64
+Generate code for 64-bit Motorola BookE.
+
+@item -mbooke, mbooke32
+Generate code for 32-bit Motorola BookE.
+
+@item -mcom
+Generate code Power/PowerPC common instructions.
+
+@item -many
+Generate code for any architecture (PWR/PWRX/PPC).
+
+@item -mregnames
+Allow symbolic names for registers.
+
+@item -mno-regnames
+Do not allow symbolic names for registers.
+
+@item -mrelocatable
+Support for GCC's -mrelocatble option.
+
+@item -mrelocatable-lib
+Support for GCC's -mrelocatble-lib option.
+
+@item -memb
+Set PPC_EMB bit in ELF flags.
+
+@item -mlittle, -mlittle-endian
+Generate code for a little endian machine.
+
+@item -mbig, -mbig-endian
+Generate code for a big endian machine.
+
+@item -msolaris
+Generate code for Solaris.
+
+@item -mno-solaris
+Do not generate code for Solaris.
+@end table