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authorNick Clifton <nickc@redhat.com>2016-03-18 17:30:12 +0000
committerNick Clifton <nickc@redhat.com>2016-03-18 17:30:12 +0000
commit30fab421840b35cdebabc01c5b90a2c1aaaa3912 (patch)
treedcfed1361b4a544d9a9754ce7f777d24ab2dda85 /gas/doc
parent87bba7a5e0858048c9b8702c147094d1a7eba92f (diff)
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Update description of AArch64 assembler directives.
gas * doc/c-aarch64.texi (AArch64 Directives): Add descriptions of .cpu, .dword, .even, .inst. .tlsdescadd, .tlsdesccall, .tlsdescldr and .xword directives.
Diffstat (limited to 'gas/doc')
-rw-r--r--gas/doc/c-aarch64.texi45
1 files changed, 41 insertions, 4 deletions
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 6a05c4f..7446655 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -273,12 +273,35 @@ incrementally to the architecture being compiled for.
This directive switches to the @code{.bss} section.
@c CCCCCCCCCCCCCCCCCCCCCCCCCC
+
+@cindex @code{.cpu} directive, AArch64
+@item .cpu @var{name}
+Set the target processor. Valid values for @var{name} are the same as
+those accepted by the @option{-mcpu=} command line option.
+
@c DDDDDDDDDDDDDDDDDDDDDDDDDD
+
+@cindex @code{.dword} directive, AArch64
+@item .dword @var{expressions}
+The @code{.dword} directive produces 64 bit values.
+
@c EEEEEEEEEEEEEEEEEEEEEEEEEE
+
+@cindex @code{.even} directive, AArch64
+@item .even
+The @code{.even} directive aligns the output on the next even byte
+boundary.
+
@c FFFFFFFFFFFFFFFFFFFFFFFFFF
@c GGGGGGGGGGGGGGGGGGGGGGGGGG
@c HHHHHHHHHHHHHHHHHHHHHHHHHH
@c IIIIIIIIIIIIIIIIIIIIIIIIII
+
+@cindex @code{.inst} directive, AArch64
+@item .inst @var{expressions}
+Inserts the expressions into the output as if they were instructions,
+rather than data.
+
@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
@c KKKKKKKKKKKKKKKKKKKKKKKKKK
@c LLLLLLLLLLLLLLLLLLLLLLLLLL
@@ -324,6 +347,18 @@ example:
@c TTTTTTTTTTTTTTTTTTTTTTTTTT
+@cindex @code{.tlsdescadd} directive, AArch64
+@item @code{.tlsdescadd}
+Emits a TLSDESC_ADD reloc on the next instruction.
+
+@cindex @code{.tlsdesccall} directive, AArch64
+@item @code{.tlsdesccall}
+Emits a TLSDESC_CALL reloc on the next instruction.
+
+@cindex @code{.tlsdescldr} directive, AArch64
+@item @code{.tlsdescldr}
+Emits a TLSDESC_LDR reloc on the next instruction.
+
@c UUUUUUUUUUUUUUUUUUUUUUUUUU
@cindex @code{.unreq} directive, AArch64
@@ -344,12 +379,14 @@ should only be done if it is really necessary.
@c WWWWWWWWWWWWWWWWWWWWWWWWWW
@c XXXXXXXXXXXXXXXXXXXXXXXXXX
-@c YYYYYYYYYYYYYYYYYYYYYYYYYY
-@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
@cindex @code{.xword} directive, AArch64
-@item .xword
-The @code{.xword} directive produces 64 bit values.
+@item .xword @var{expressions}
+The @code{.xword} directive produces 64 bit values. This is the same
+as the @code{.dword} directive.
+
+@c YYYYYYYYYYYYYYYYYYYYYYYYYY
+@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
@end table