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author | Ilya Tocar <ilya.tocar@intel.com> | 2014-09-16 13:33:47 +0400 |
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committer | H.J. Lu <hjl.tools@gmail.com> | 2014-09-16 08:45:28 -0700 |
commit | d3d3c6db1a3de87d5df6900f3be0557c33fa23b3 (patch) | |
tree | 338b7e787689246c1ef99405e96d68e3a6ef9602 /gas/doc | |
parent | deb8ff2b7afbdfae3c10def598977c4690f7056b (diff) | |
download | gdb-d3d3c6db1a3de87d5df6900f3be0557c33fa23b3.zip gdb-d3d3c6db1a3de87d5df6900f3be0557c33fa23b3.tar.gz gdb-d3d3c6db1a3de87d5df6900f3be0557c33fa23b3.tar.bz2 |
Add -mevexrcig={rne|rd|ru|rz} option to x86 assembler.
It is used to control which value is encoded in rounding control bits
for SAE-only EVEX instructions.
gas/
* config/tc-i386.c (evexrcig): New.
(build_evex_prefix): Force rounding bits.
(OPTION_MEVEXRCIG): New.
(md_longopts): Add mevexrcig.
(md_parse_option): Handle OPTION_MEVEXRCIG.
(md_show_usage): Document mevexrcig.
* doc/c-i386.texi (mevexrcig): Document new option.
gas/testsuite/
* gas/i386/avx512dq-rcig.s: New.
* gas/i386/avx512dq-rcigrd-intel.d: Likewise.
* gas/i386/avx512dq-rcigrd.d: Likewise.
* gas/i386/avx512dq-rcigrne-intel.d: Likewise.
* gas/i386/avx512dq-rcigrne.d: Likewise.
* gas/i386/avx512dq-rcigru-intel.d: Likewise.
* gas/i386/avx512dq-rcigru.d: Likewise.
* gas/i386/avx512dq-rcigrz-intel.d: Likewise.
* gas/i386/avx512dq-rcigrz.d: Likewise.
* gas/i386/avx512er-rcig.s: Likewise.
* gas/i386/avx512er-rcigrd-intel.d: Likewise.
* gas/i386/avx512er-rcigrd.d: Likewise.
* gas/i386/avx512er-rcigrne-intel.d: Likewise.
* gas/i386/avx512er-rcigrne.d: Likewise.
* gas/i386/avx512er-rcigru-intel.d: Likewise.
* gas/i386/avx512er-rcigru.d: Likewise.
* gas/i386/avx512er-rcigrz-intel.d: Likewise.
* gas/i386/avx512er-rcigrz.d: Likewise.
* gas/i386/avx512f-rcig.s: Likewise.
* gas/i386/avx512f-rcigrd-intel.d: Likewise.
* gas/i386/avx512f-rcigrd.d: Likewise.
* gas/i386/avx512f-rcigrne-intel.d: Likewise.
* gas/i386/avx512f-rcigrne.d: Likewise.
* gas/i386/avx512f-rcigru-intel.d: Likewise.
* gas/i386/avx512f-rcigru.d: Likewise.
* gas/i386/avx512f-rcigrz-intel.d: Likewise.
* gas/i386/avx512f-rcigrz.d: Likewise.
* gas/i386/x86-64-avx512dq-rcig.s: Likewise.
* gas/i386/x86-64-avx512dq-rcigrd-intel.d: Likewise.
* gas/i386/x86-64-avx512dq-rcigrd.d: Likewise.
* gas/i386/x86-64-avx512dq-rcigrne-intel.d: Likewise.
* gas/i386/x86-64-avx512dq-rcigrne.d: Likewise.
* gas/i386/x86-64-avx512dq-rcigru-intel.d: Likewise.
* gas/i386/x86-64-avx512dq-rcigru.d: Likewise.
* gas/i386/x86-64-avx512dq-rcigrz-intel.d: Likewise.
* gas/i386/x86-64-avx512dq-rcigrz.d: Likewise.
* gas/i386/x86-64-avx512er-rcig.s: Likewise.
* gas/i386/x86-64-avx512er-rcigrd-intel.d: Likewise.
* gas/i386/x86-64-avx512er-rcigrd.d: Likewise.
* gas/i386/x86-64-avx512er-rcigrne-intel.d: Likewise.
* gas/i386/x86-64-avx512er-rcigrne.d: Likewise.
* gas/i386/x86-64-avx512er-rcigru-intel.d: Likewise.
* gas/i386/x86-64-avx512er-rcigru.d: Likewise.
* gas/i386/x86-64-avx512er-rcigrz-intel.d: Likewise.
* gas/i386/x86-64-avx512er-rcigrz.d: Likewise.
* gas/i386/x86-64-avx512f-rcig.s: Likewise.
* gas/i386/x86-64-avx512f-rcigrd-intel.d: Likewise.
* gas/i386/x86-64-avx512f-rcigrd.d: Likewise.
* gas/i386/x86-64-avx512f-rcigrne-intel.d: Likewise.
* gas/i386/x86-64-avx512f-rcigrne.d: Likewise.
* gas/i386/x86-64-avx512f-rcigru-intel.d: Likewise.
* gas/i386/x86-64-avx512f-rcigru.d: Likewise.
* gas/i386/x86-64-avx512f-rcigrz-intel.d: Likewise.
* gas/i386/x86-64-avx512f-rcigrz.d: Likewise.
* gas/i386/i386.exp: Run new tests.
Diffstat (limited to 'gas/doc')
-rw-r--r-- | gas/doc/c-i386.texi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 0c2e134..75cd6b1 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -303,6 +303,19 @@ single-thread computers @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual, which is the default. +@cindex @samp{-mevexrcig=} option, i386 +@cindex @samp{-mevexrcig=} option, x86-64 +@item -mevexrcig=@var{rne} +@itemx -mevexrcig=@var{rd} +@itemx -mevexrcig=@var{ru} +@itemx -mevexrcig=@var{rz} +These options control how the assembler should encode SAE-only +EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits +of EVEX instruction with 00, which is the default. +@option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}} +and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions +with 01, 10 and 11 RC bits, respectively. + @end table @c man end |