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authorNick Clifton <nickc@redhat.com>1999-07-05 07:39:01 +0000
committerNick Clifton <nickc@redhat.com>1999-07-05 07:39:01 +0000
commit49a5575c32d7c48c0f17b88cdd2cab6bb2db10b5 (patch)
treebc74366cdae5a66e221988e59ced3d3861fe6d52 /gas/doc
parent849a0ebfb768f7ccd94741ac6af7d14ab0223dca (diff)
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Add support for armv5 architecture
Add ADRL pseudo op.
Diffstat (limited to 'gas/doc')
-rw-r--r--gas/doc/c-arm.texi53
1 files changed, 47 insertions, 6 deletions
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index b94fb2a..1538ac9 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -29,12 +29,12 @@
@cindex options for ARM (none)
@table @code
@cindex @code{-marm} command line option, ARM
-@item -marm @var{[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmistrongarm|strongarm110|strongarm1100]}
+@item -marm @var{[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920||strongarm|strongarm110|strongarm1100]}
This option specifies the target processor. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor.
@cindex @code{-marmv} command line option, ARM
-@item -marmv @var{[2|2a|3|3m|4|4t]}
+@item -marmv @var{[2|2a|3|3m|4|4t|5|5t]}
This option specifies the target architecture. The assembler will issue
an error message if an attempt is made to assemble an instruction which
will not execute on the target architecture.
@@ -184,13 +184,23 @@ This is a synonym for .ltorg.
@cindex ARM opcodes
@cindex opcodes for ARM
-@code{@value{AS}} implements all the standard ARM opcodes.
+@code{@value{AS}} implements all the standard ARM opcodes. It also
+implements several pseudo opcodes, including several synthetic load
+instructions.
-*TODO* Document the pseudo-ops (adr, nop)
+@table @code
+
+@cindex @code{NOP} pseudo op, ARM
+@item NOP
+@smallexample
+ nop
+@end smallexample
-GAS for the ARM supports a synthetic register load instruction whoes
-syntax is:
+This pseudo op will always evaluate to a legal ARM instruction that does
+nothing. Currently it will evaluate to MOV r0, r0.
+@cindex @code{LDR reg,=<label>} pseudo op, ARM
+@item LDR
@smallexample
ldr <register> , = <expression>
@end smallexample
@@ -201,6 +211,37 @@ constant can be generated by either of these instructions. Otherwise
the constant will be placed into the nearest literal pool (if it not
already there) and a PC relative LDR instruction will be generated.
+@cindex @code{ADR reg,<label>} pseudo op, ARM
+@item ADR
+@smallexample
+ adr <register> <label>
+@end smallexample
+
+This instruction will load the address of @var{label} into the indicated
+register. The instruction will evaluate to a PC relative ADD or SUB
+instruction depending upon where the label is located. If the label is
+out of range, or if it is not defined in the same file (and section) as
+the ADR instruction, then an error will be generated. This instruction
+will not make use of the literal pool.
+
+@cindex @code{ADRL reg,<label>} pseudo op, ARM
+@item ADRL
+@smallexample
+ adrl <register> <label>
+@end smallexample
+
+This instruction will load the address of @var{label} into the indicated
+register. The instruction will evaluate to one or two a PC relative ADD
+or SUB instructions depending upon where the label is located. If a
+second instruction is not needed a NOP instruction will be generated in
+its place, so that this instruction is always 8 bytes long.
+
+If the label is out of range, or if it is not defined in the same file
+(and section) as the ADRL instruction, then an error will be generated.
+This instruction will not make use of the literal pool.
+
+@end table
+
For information on the ARM or Thumb instruction sets, see @cite{ARM
Software Development Toolkit Reference Manual}, Advanced RISC Machines
Ltd.