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authorIan Lance Taylor <ian@airs.com>1995-08-10 21:18:21 +0000
committerIan Lance Taylor <ian@airs.com>1995-08-10 21:18:21 +0000
commit79e15b8a98b30ba31dbd923baffc2e6c9487cc06 (patch)
tree49cb21e618bb6f0804355c0681ee3b2da6f64e06 /gas/doc
parent5357b554ba842e5ec4e71a373fd3a44547d5fed7 (diff)
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* doc/as.texinfo: Add documentation for MRI compatibility mode.
* doc/as.1: Likewise.
Diffstat (limited to 'gas/doc')
-rw-r--r--gas/doc/as.14
-rw-r--r--gas/doc/as.texinfo3552
2 files changed, 135 insertions, 3421 deletions
diff --git a/gas/doc/as.1 b/gas/doc/as.1
index 09e4c5d..6b977fe 100644
--- a/gas/doc/as.1
+++ b/gas/doc/as.1
@@ -19,6 +19,7 @@ GNU as\-\-the portable GNU assembler.
\&\|]
.RB "[\|" \-K "\|]"
.RB "[\|" \-L "\|]"
+.RB "[\|" \-M\ |\ \-\-mri "\|]"
.RB "[\|" \-o
.I objfile\c
\&\|]
@@ -164,6 +165,9 @@ Keep (in symbol table) local symbols, starting with `\|\c
.B L\c
\|'
.TP
+.B \-M, \-\-mri
+Assemble in MRI compatibility mode.
+.TP
.BI "\-o\ " objfile
Name the object-file output from \c
.B as
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index 91eda83..0546373 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -1,5 +1,5 @@
\input texinfo @c -*-Texinfo-*-
-@c Copyright (c) 1991 1992 1993 1994 Free Software Foundation, Inc.
+@c Copyright (c) 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
@c UPDATE!! On future updates--
@c (1) check for new machine-dep cmdline options in
@c md_parse_option definitions in config/tc-*.c
@@ -82,7 +82,7 @@ END-INFO-DIR-ENTRY
@ifinfo
This file documents the GNU Assembler "@value{AS}".
-Copyright (C) 1991, 1992, 1993, 1994 Free Software Foundation, Inc.
+Copyright (C) 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
Permission is granted to make and distribute verbatim copies of
this manual provided the copyright notice and this permission notice
@@ -846,6 +846,7 @@ assembler.)
@end ifset
* L:: -L to retain local labels
+* M:: -M or --mri to assemble in MRI compatibility mode
* o:: -o to name the object file
* R:: -R to join data and text sections
* statistics:: --statistics to see statistics about assembly
@@ -980,6 +981,119 @@ On the ARC local labels begin with @samp{.L}.
@end ifset
@c end-sanitize-arc
+@node M
+@section Assemble in MRI Compatibility Mode: @code{-M}
+
+@kindex -M
+@cindex MRI compatibility mode
+The @code{-M} or @code{--mri} option selects MRI compatibility mode. This
+changes the syntax and pseudo-op handling of @code{@value{AS}} to make it
+compatible with the @code{ASM68K} assembler from Microtec Research. The exact
+nature of the MRI syntax will not be documented here; see the MRI manuals for
+more information. The purpose of this option is to permit assembling existing
+MRI assembler code using @code{@value{AS}}.
+
+The MRI compatibility is not complete. Certain operations of the MRI assembler
+depend upon its object file format, and can not be supported using other object
+file formats. Supporting these would require enhancing each object file format
+individually. These are:
+
+@itemize @bullet
+@item global symbols in common section
+
+The MRI assembler supports common sections which are merged by the linker.
+Other object file formats do not support this. @code{@value{AS}} handles
+common sections by treating them as a single common symbol. It permits local
+symbols to be defined within a common section, but it can not support global
+symbols, since it has no way to describe them.
+
+@item complex relocations
+
+The MRI assembler supports relocations against a negated section address, and
+relocations which combine the start addresses of two or more sections. These
+are not support by other object file formats.
+
+@item @code{END} pseudo-op specifying start address
+
+The MRI @code{END} pseudo-op permits the specification of a start address.
+This is not supported by other object file formats. The start address may
+instead be specified using the @code{-e} option to the linker, or in a linker
+script.
+
+@item @code{IDNT} and @code{NAME} pseudo-ops
+
+The MRI @code{IDNT} and @code{NAME} pseudo-ops assign a module name to the
+output file. This is not supported by other object file formats.
+
+@item @code{ORG} pseudo-op
+
+The MRI @code{ORG} pseudo-op begins an absolute section at a given address.
+This differs from the usual @code{@value{AS}} @code{.org} pseudo-op, which
+changes the location within the current section. Absolute sections are not
+supported by other object file formats. The address of a section may be
+assigned within a linker script.
+@end itemize
+
+There are some other features of the MRI assembler which are not supported by
+@code{@value{AS}}, typically either because they are difficult or because they
+seem of little consequence. Some of these may be supported in future releases.
+
+@itemize @bullet
+
+@item @code{.STARTOF.} and @code{.SIZEOF.} operators
+
+The @code{.STARTOF.} and @code{.SIZEOF.} operators are not supported. They
+require linker support.
+
+@item EBCDIC strings
+
+EBCDIC strings are not supported.
+
+@item packed binary coded decimal
+
+Packed binary coded decimal is not supported. This means that the @code{DC.P}
+and @code{DCB.P} pseudo-ops are not supported.
+
+@item @code{FEQU} pseudo-op
+
+The @code{FEQU} pseudo-op is not supported.
+
+@item @code{NOOBJ} pseudo-op
+
+The @code{NOOBJ} pseudo-op is not supported.
+
+@item @code{OPT} branch control options
+
+The @code{OPT} branch control options---@code{B}, @code{BRS}, @code{BRB},
+@code{BRL}, and @code{BRW}---are ignored. @code{@value{AS}} automatically
+relaxes all branches, whether forward or backward, to an appropriate size, so
+these options serve no purpose.
+
+@item @code{OPT} list control options
+
+The following @code{OPT} list control options are ignored: @code{C},
+@code{CEX}, @code{CL}, @code{CRE}, @code{E}, @code{G}, @code{I}, @code{M},
+@code{MEX}, @code{MC}, @code{MD}, @code{X}.
+
+@item other @code{OPT} options
+
+The following @code{OPT} options are ignored: @code{NEST}, @code{O},
+@code{OLD}, @code{OP}, @code{P}, @code{PCO}, @code{PCR}, @code{PCS}, @code{R}.
+
+@item @code{OPT} @code{D} option is default
+
+The @code{OPT} @code{D} option is the default, unlike the MRI assembler.
+@code{OPT NOD} may be used to turn it off.
+
+@item @code{XREF} pseudo-op.
+
+The @code{XREF} pseudo-op is ignored.
+
+@item macros
+
+Macros are not supported directly, but are supported by @code{gasp}.
+@end itemize
+
@node o
@section Name the Object File: @code{-o}
@@ -4075,506 +4189,13 @@ This must be followed by the desired cpu. It must be one of
@c end-sanitize-arc
@ifset VAX
-@ifset GENERIC
-@node Vax-Dependent
-@chapter VAX Dependent Features
-@cindex VAX support
-
-@end ifset
-@ifclear GENERIC
-@node Machine Dependencies
-@chapter VAX Dependent Features
-@cindex VAX support
-
-@end ifclear
-
-@menu
-* Vax-Opts:: VAX Command-Line Options
-* VAX-float:: VAX Floating Point
-* VAX-directives:: Vax Machine Directives
-* VAX-opcodes:: VAX Opcodes
-* VAX-branch:: VAX Branch Improvement
-* VAX-operands:: VAX Operands
-* VAX-no:: Not Supported on VAX
-@end menu
-
-
-@node Vax-Opts
-@section VAX Command-Line Options
-
-@cindex command-line options ignored, VAX
-@cindex VAX command-line options ignored
-The Vax version of @code{@value{AS}} accepts any of the following options,
-gives a warning message that the option was ignored and proceeds.
-These options are for compatibility with scripts designed for other
-people's assemblers.
-
-@table @code
-@item @code{-D} (Debug)
-@itemx @code{-S} (Symbol Table)
-@itemx @code{-T} (Token Trace)
-@cindex @code{-D}, ignored on VAX
-@cindex @code{-S}, ignored on VAX
-@cindex @code{-T}, ignored on VAX
-These are obsolete options used to debug old assemblers.
-
-@item @code{-d} (Displacement size for JUMPs)
-@cindex @code{-d}, VAX option
-This option expects a number following the @samp{-d}. Like options
-that expect filenames, the number may immediately follow the
-@samp{-d} (old standard) or constitute the whole of the command line
-argument that follows @samp{-d} (@sc{gnu} standard).
-
-@item @code{-V} (Virtualize Interpass Temporary File)
-@cindex @code{-V}, redundant on VAX
-Some other assemblers use a temporary file. This option
-commanded them to keep the information in active memory rather
-than in a disk file. @code{@value{AS}} always does this, so this
-option is redundant.
-
-@item @code{-J} (JUMPify Longer Branches)
-@cindex @code{-J}, ignored on VAX
-Many 32-bit computers permit a variety of branch instructions
-to do the same job. Some of these instructions are short (and
-fast) but have a limited range; others are long (and slow) but
-can branch anywhere in virtual memory. Often there are 3
-flavors of branch: short, medium and long. Some other
-assemblers would emit short and medium branches, unless told by
-this option to emit short and long branches.
-
-@item @code{-t} (Temporary File Directory)
-@cindex @code{-t}, ignored on VAX
-Some other assemblers may use a temporary file, and this option
-takes a filename being the directory to site the temporary
-file. Since @code{@value{AS}} does not use a temporary disk file, this
-option makes no difference. @samp{-t} needs exactly one
-filename.
-@end table
-
-@cindex VMS (VAX) options
-@cindex options for VAX/VMS
-@cindex VAX/VMS options
-@cindex @code{-h} option, VAX/VMS
-@cindex @code{-+} option, VAX/VMS
-@cindex Vax-11 C compatibility
-@cindex symbols with lowercase, VAX/VMS
-@c FIXME! look into "I think" below, correct if needed, delete.
-The Vax version of the assembler accepts two options when
-compiled for VMS. They are @samp{-h}, and @samp{-+}. The
-@samp{-h} option prevents @code{@value{AS}} from modifying the
-symbol-table entries for symbols that contain lowercase
-characters (I think). The @samp{-+} option causes @code{@value{AS}} to
-print warning messages if the FILENAME part of the object file,
-or any symbol name is larger than 31 characters. The @samp{-+}
-option also inserts some code following the @samp{_main}
-symbol so that the object file is compatible with Vax-11
-"C".
-
-@node VAX-float
-@section VAX Floating Point
-
-@cindex VAX floating point
-@cindex floating point, VAX
-Conversion of flonums to floating point is correct, and
-compatible with previous assemblers. Rounding is
-towards zero if the remainder is exactly half the least significant bit.
-
-@code{D}, @code{F}, @code{G} and @code{H} floating point formats
-are understood.
-
-Immediate floating literals (@emph{e.g.} @samp{S`$6.9})
-are rendered correctly. Again, rounding is towards zero in the
-boundary case.
-
-@cindex @code{float} directive, VAX
-@cindex @code{double} directive, VAX
-The @code{.float} directive produces @code{f} format numbers.
-The @code{.double} directive produces @code{d} format numbers.
-
-@node VAX-directives
-@section Vax Machine Directives
-
-@cindex machine directives, VAX
-@cindex VAX machine directives
-The Vax version of the assembler supports four directives for
-generating Vax floating point constants. They are described in the
-table below.
-
-@cindex wide floating point directives, VAX
-@table @code
-@item .dfloat
-@cindex @code{dfloat} directive, VAX
-This expects zero or more flonums, separated by commas, and
-assembles Vax @code{d} format 64-bit floating point constants.
-
-@item .ffloat
-@cindex @code{ffloat} directive, VAX
-This expects zero or more flonums, separated by commas, and
-assembles Vax @code{f} format 32-bit floating point constants.
-
-@item .gfloat
-@cindex @code{gfloat} directive, VAX
-This expects zero or more flonums, separated by commas, and
-assembles Vax @code{g} format 64-bit floating point constants.
-
-@item .hfloat
-@cindex @code{hfloat} directive, VAX
-This expects zero or more flonums, separated by commas, and
-assembles Vax @code{h} format 128-bit floating point constants.
-
-@end table
-
-@node VAX-opcodes
-@section VAX Opcodes
-
-@cindex VAX opcode mnemonics
-@cindex opcode mnemonics, VAX
-@cindex mnemonics for opcodes, VAX
-All DEC mnemonics are supported. Beware that @code{case@dots{}}
-instructions have exactly 3 operands. The dispatch table that
-follows the @code{case@dots{}} instruction should be made with
-@code{.word} statements. This is compatible with all unix
-assemblers we know of.
-
-@node VAX-branch
-@section VAX Branch Improvement
-
-@cindex VAX branch improvement
-@cindex branch improvement, VAX
-@cindex pseudo-ops for branch, VAX
-Certain pseudo opcodes are permitted. They are for branch
-instructions. They expand to the shortest branch instruction that
-reaches the target. Generally these mnemonics are made by
-substituting @samp{j} for @samp{b} at the start of a DEC mnemonic.
-This feature is included both for compatibility and to help
-compilers. If you do not need this feature, avoid these
-opcodes. Here are the mnemonics, and the code they can expand into.
-
-@table @code
-@item jbsb
-@samp{Jsb} is already an instruction mnemonic, so we chose @samp{jbsb}.
-@table @asis
-@item (byte displacement)
-@kbd{bsbb @dots{}}
-@item (word displacement)
-@kbd{bsbw @dots{}}
-@item (long displacement)
-@kbd{jsb @dots{}}
-@end table
-@item jbr
-@itemx jr
-Unconditional branch.
-@table @asis
-@item (byte displacement)
-@kbd{brb @dots{}}
-@item (word displacement)
-@kbd{brw @dots{}}
-@item (long displacement)
-@kbd{jmp @dots{}}
-@end table
-@item j@var{COND}
-@var{COND} may be any one of the conditional branches
-@code{neq}, @code{nequ}, @code{eql}, @code{eqlu}, @code{gtr},
-@code{geq}, @code{lss}, @code{gtru}, @code{lequ}, @code{vc}, @code{vs},
-@code{gequ}, @code{cc}, @code{lssu}, @code{cs}.
-@var{COND} may also be one of the bit tests
-@code{bs}, @code{bc}, @code{bss}, @code{bcs}, @code{bsc}, @code{bcc},
-@code{bssi}, @code{bcci}, @code{lbs}, @code{lbc}.
-@var{NOTCOND} is the opposite condition to @var{COND}.
-@table @asis
-@item (byte displacement)
-@kbd{b@var{COND} @dots{}}
-@item (word displacement)
-@kbd{b@var{NOTCOND} foo ; brw @dots{} ; foo:}
-@item (long displacement)
-@kbd{b@var{NOTCOND} foo ; jmp @dots{} ; foo:}
-@end table
-@item jacb@var{X}
-@var{X} may be one of @code{b d f g h l w}.
-@table @asis
-@item (word displacement)
-@kbd{@var{OPCODE} @dots{}}
-@item (long displacement)
-@example
-@var{OPCODE} @dots{}, foo ;
-brb bar ;
-foo: jmp @dots{} ;
-bar:
-@end example
-@end table
-@item jaob@var{YYY}
-@var{YYY} may be one of @code{lss leq}.
-@item jsob@var{ZZZ}
-@var{ZZZ} may be one of @code{geq gtr}.
-@table @asis
-@item (byte displacement)
-@kbd{@var{OPCODE} @dots{}}
-@item (word displacement)
-@example
-@var{OPCODE} @dots{}, foo ;
-brb bar ;
-foo: brw @var{destination} ;
-bar:
-@end example
-@item (long displacement)
-@example
-@var{OPCODE} @dots{}, foo ;
-brb bar ;
-foo: jmp @var{destination} ;
-bar:
-@end example
-@end table
-@item aobleq
-@itemx aoblss
-@itemx sobgeq
-@itemx sobgtr
-@table @asis
-@item (byte displacement)
-@kbd{@var{OPCODE} @dots{}}
-@item (word displacement)
-@example
-@var{OPCODE} @dots{}, foo ;
-brb bar ;
-foo: brw @var{destination} ;
-bar:
-@end example
-@item (long displacement)
-@example
-@var{OPCODE} @dots{}, foo ;
-brb bar ;
-foo: jmp @var{destination} ;
-bar:
-@end example
-@end table
-@end table
-
-@node VAX-operands
-@section VAX Operands
-
-@cindex VAX operand notation
-@cindex operand notation, VAX
-@cindex immediate character, VAX
-@cindex VAX immediate character
-The immediate character is @samp{$} for Unix compatibility, not
-@samp{#} as DEC writes it.
-
-@cindex indirect character, VAX
-@cindex VAX indirect character
-The indirect character is @samp{*} for Unix compatibility, not
-@samp{@@} as DEC writes it.
-
-@cindex displacement sizing character, VAX
-@cindex VAX displacement sizing character
-The displacement sizing character is @samp{`} (an accent grave) for
-Unix compatibility, not @samp{^} as DEC writes it. The letter
-preceding @samp{`} may have either case. @samp{G} is not
-understood, but all other letters (@code{b i l s w}) are understood.
-
-@cindex register names, VAX
-@cindex VAX register names
-Register names understood are @code{r0 r1 r2 @dots{} r15 ap fp sp
-pc}. Upper and lower case letters are equivalent.
-
-For instance
-@smallexample
-tstb *w`$4(r5)
-@end smallexample
-
-Any expression is permitted in an operand. Operands are comma
-separated.
-
-@c There is some bug to do with recognizing expressions
-@c in operands, but I forget what it is. It is
-@c a syntax clash because () is used as an address mode
-@c and to encapsulate sub-expressions.
-
-@node VAX-no
-@section Not Supported on VAX
-
-@cindex VAX bitfields not supported
-@cindex bitfields, not supported on VAX
-Vax bit fields can not be assembled with @code{@value{AS}}. Someone
-can add the required code if they really need it.
-
+@include c-vax.texi
@end ifset
@ifset A29K
-@ifset GENERIC
-@page
-@node AMD29K-Dependent
-@chapter AMD 29K Dependent Features
+@include c-a29k.texi
@end ifset
-@ifclear GENERIC
-@node Machine Dependencies
-@chapter AMD 29K Dependent Features
-@end ifclear
-@cindex AMD 29K support
-@cindex 29K support
-@menu
-* AMD29K Options:: Options
-* AMD29K Syntax:: Syntax
-* AMD29K Floating Point:: Floating Point
-* AMD29K Directives:: AMD 29K Machine Directives
-* AMD29K Opcodes:: Opcodes
-@end menu
-
-@node AMD29K Options
-@section Options
-@cindex AMD 29K options (none)
-@cindex options for AMD29K (none)
-@code{@value{AS}} has no additional command-line options for the AMD
-29K family.
-
-@node AMD29K Syntax
-@section Syntax
-@menu
-* AMD29K-Chars:: Special Characters
-* AMD29K-Regs:: Register Names
-@end menu
-
-@node AMD29K-Chars
-@subsection Special Characters
-
-@cindex line comment character, AMD 29K
-@cindex AMD 29K line comment character
-@samp{;} is the line comment character.
-
-@cindex line separator, AMD 29K
-@cindex AMD 29K line separator
-@cindex statement separator, AMD 29K
-@cindex AMD 29K statement separator
-@samp{@@} can be used instead of a newline to separate statements.
-
-@cindex identifiers, AMD 29K
-@cindex AMD 29K identifiers
-The character @samp{?} is permitted in identifiers (but may not begin
-an identifier).
-
-@node AMD29K-Regs
-@subsection Register Names
-
-@cindex AMD 29K register names
-@cindex register names, AMD 29K
-General-purpose registers are represented by predefined symbols of the
-form @samp{GR@var{nnn}} (for global registers) or @samp{LR@var{nnn}}
-(for local registers), where @var{nnn} represents a number between
-@code{0} and @code{127}, written with no leading zeros. The leading
-letters may be in either upper or lower case; for example, @samp{gr13}
-and @samp{LR7} are both valid register names.
-
-You may also refer to general-purpose registers by specifying the
-register number as the result of an expression (prefixed with @samp{%%}
-to flag the expression as a register number):
-@smallexample
-%%@var{expression}
-@end smallexample
-@noindent
----where @var{expression} must be an absolute expression evaluating to a
-number between @code{0} and @code{255}. The range [0, 127] refers to
-global registers, and the range [128, 255] to local registers.
-
-@cindex special purpose registers, AMD 29K
-@cindex AMD 29K special purpose registers
-@cindex protected registers, AMD 29K
-@cindex AMD 29K protected registers
-In addition, @code{@value{AS}} understands the following protected
-special-purpose register names for the AMD 29K family:
-
-@smallexample
- vab chd pc0
- ops chc pc1
- cps rbp pc2
- cfg tmc mmu
- cha tmr lru
-@end smallexample
-
-These unprotected special-purpose register names are also recognized:
-@smallexample
- ipc alu fpe
- ipa bp inte
- ipb fc fps
- q cr exop
-@end smallexample
-
-@node AMD29K Floating Point
-@section Floating Point
-
-@cindex floating point, AMD 29K (@sc{ieee})
-@cindex AMD 29K floating point (@sc{ieee})
-The AMD 29K family uses @sc{ieee} floating-point numbers.
-
-@node AMD29K Directives
-@section AMD 29K Machine Directives
-
-@cindex machine directives, AMD 29K
-@cindex AMD 29K machine directives
-@table @code
-@item .block @var{size} , @var{fill}
-@cindex @code{block} directive, AMD 29K
-This directive emits @var{size} bytes, each of value @var{fill}. Both
-@var{size} and @var{fill} are absolute expressions. If the comma
-and @var{fill} are omitted, @var{fill} is assumed to be zero.
-
-In other versions of the @sc{gnu} assembler, this directive is called
-@samp{.space}.
-@end table
-
-@table @code
-@item .cputype
-@cindex @code{cputype} directive, AMD 29K
-This directive is ignored; it is accepted for compatibility with other
-AMD 29K assemblers.
-
-@item .file
-@cindex @code{file} directive, AMD 29K
-This directive is ignored; it is accepted for compatibility with other
-AMD 29K assemblers.
-
-@quotation
-@emph{Warning:} in other versions of the @sc{gnu} assembler, @code{.file} is
-used for the directive called @code{.app-file} in the AMD 29K support.
-@end quotation
-
-@item .line
-@cindex @code{line} directive, AMD 29K
-This directive is ignored; it is accepted for compatibility with other
-AMD 29K assemblers.
-
-@ignore
-@c since we're ignoring .lsym...
-@item .reg @var{symbol}, @var{expression}
-@cindex @code{reg} directive, AMD 29K
-@code{.reg} has the same effect as @code{.lsym}; @pxref{Lsym,,@code{.lsym}}.
-@end ignore
-
-@item .sect
-@cindex @code{sect} directive, AMD 29K
-This directive is ignored; it is accepted for compatibility with other
-AMD 29K assemblers.
-
-@item .use @var{section name}
-@cindex @code{use} directive, AMD 29K
-Establishes the section and subsection for the following code;
-@var{section name} may be one of @code{.text}, @code{.data},
-@code{.data1}, or @code{.lit}. With one of the first three @var{section
-name} options, @samp{.use} is equivalent to the machine directive
-@var{section name}; the remaining case, @samp{.use .lit}, is the same as
-@samp{.data 200}.
-@end table
-
-@node AMD29K Opcodes
-@section Opcodes
-
-@cindex AMD 29K opcodes
-@cindex opcodes for AMD 29K
-@code{@value{AS}} implements all the standard AMD 29K opcodes. No
-additional pseudo-instructions are needed on this family.
-
-For information on the 29K machine instruction set, see @cite{Am29000
-User's Manual}, Advanced Micro Devices, Inc.
-
-@end ifset
@ifset Hitachi-all
@ifclear GENERIC
@node Machine Dependencies
@@ -4595,1825 +4216,29 @@ family.
@end ifset
@ifset H8/300
-@ifset GENERIC
-@page
-@end ifset
-@node H8/300-Dependent
-@chapter H8/300 Dependent Features
-
-@cindex H8/300 support
-@menu
-* H8/300 Options:: Options
-* H8/300 Syntax:: Syntax
-* H8/300 Floating Point:: Floating Point
-* H8/300 Directives:: H8/300 Machine Directives
-* H8/300 Opcodes:: Opcodes
-@end menu
-
-@node H8/300 Options
-@section Options
-
-@cindex H8/300 options (none)
-@cindex options, H8/300 (none)
-@code{@value{AS}} has no additional command-line options for the Hitachi
-H8/300 family.
-
-@node H8/300 Syntax
-@section Syntax
-@menu
-* H8/300-Chars:: Special Characters
-* H8/300-Regs:: Register Names
-* H8/300-Addressing:: Addressing Modes
-@end menu
-
-@node H8/300-Chars
-@subsection Special Characters
-
-@cindex line comment character, H8/300
-@cindex H8/300 line comment character
-@samp{;} is the line comment character.
-
-@cindex line separator, H8/300
-@cindex statement separator, H8/300
-@cindex H8/300 line separator
-@samp{$} can be used instead of a newline to separate statements.
-Therefore @emph{you may not use @samp{$} in symbol names} on the H8/300.
-
-@node H8/300-Regs
-@subsection Register Names
-
-@cindex H8/300 registers
-@cindex register names, H8/300
-You can use predefined symbols of the form @samp{r@var{n}h} and
-@samp{r@var{n}l} to refer to the H8/300 registers as sixteen 8-bit
-general-purpose registers. @var{n} is a digit from @samp{0} to
-@samp{7}); for instance, both @samp{r0h} and @samp{r7l} are valid
-register names.
-
-You can also use the eight predefined symbols @samp{r@var{n}} to refer
-to the H8/300 registers as 16-bit registers (you must use this form for
-addressing).
-
-On the H8/300H, you can also use the eight predefined symbols
-@samp{er@var{n}} (@samp{er0} @dots{} @samp{er7}) to refer to the 32-bit
-general purpose registers.
-
-The two control registers are called @code{pc} (program counter; a
-16-bit register, except on the H8/300H where it is 24 bits) and
-@code{ccr} (condition code register; an 8-bit register). @code{r7} is
-used as the stack pointer, and can also be called @code{sp}.
-
-@node H8/300-Addressing
-@subsection Addressing Modes
-
-@cindex addressing modes, H8/300
-@cindex H8/300 addressing modes
-@value{AS} understands the following addressing modes for the H8/300:
-@table @code
-@item r@var{n}
-Register direct
-
-@item @@r@var{n}
-Register indirect
-
-@item @@(@var{d}, r@var{n})
-@itemx @@(@var{d}:16, r@var{n})
-@itemx @@(@var{d}:24, r@var{n})
-Register indirect: 16-bit or 24-bit displacement @var{d} from register
-@var{n}. (24-bit displacements are only meaningful on the H8/300H.)
-
-@item @@r@var{n}+
-Register indirect with post-increment
-
-@item @@-r@var{n}
-Register indirect with pre-decrement
-
-@item @code{@@}@var{aa}
-@itemx @code{@@}@var{aa}:8
-@itemx @code{@@}@var{aa}:16
-@itemx @code{@@}@var{aa}:24
-Absolute address @code{aa}. (The address size @samp{:24} only makes
-sense on the H8/300H.)
-
-@item #@var{xx}
-@itemx #@var{xx}:8
-@itemx #@var{xx}:16
-@itemx #@var{xx}:32
-Immediate data @var{xx}. You may specify the @samp{:8}, @samp{:16}, or
-@samp{:32} for clarity, if you wish; but @code{@value{AS}} neither
-requires this nor uses it---the data size required is taken from
-context.
-
-@item @code{@@}@code{@@}@var{aa}
-@itemx @code{@@}@code{@@}@var{aa}:8
-Memory indirect. You may specify the @samp{:8} for clarity, if you
-wish; but @code{@value{AS}} neither requires this nor uses it.
-@end table
-
-@node H8/300 Floating Point
-@section Floating Point
-
-@cindex floating point, H8/300 (@sc{ieee})
-@cindex H8/300 floating point (@sc{ieee})
-The H8/300 family has no hardware floating point, but the @code{.float}
-directive generates @sc{ieee} floating-point numbers for compatibility
-with other development tools.
-
-@page
-@node H8/300 Directives
-@section H8/300 Machine Directives
-
-@cindex H8/300 machine directives (none)
-@cindex machine directives, H8/300 (none)
-@cindex @code{word} directive, H8/300
-@cindex @code{int} directive, H8/300
-@code{@value{AS}} has only one machine-dependent directive for the
-H8/300:
-
-@table @code
-@cindex H8/300H, assembling for
-@item .h8300h
-Recognize and emit additional instructions for the H8/300H variant, and
-also make @code{.int} emit 32-bit numbers rather than the usual (16-bit)
-for the H8/300 family.
-@end table
-
-On the H8/300 family (including the H8/300H) @samp{.word} directives
-generate 16-bit numbers.
-
-@node H8/300 Opcodes
-@section Opcodes
-
-@cindex H8/300 opcode summary
-@cindex opcode summary, H8/300
-@cindex mnemonics, H8/300
-@cindex instruction summary, H8/300
-For detailed information on the H8/300 machine instruction set, see
-@cite{H8/300 Series Programming Manual} (Hitachi ADE--602--025). For
-information specific to the H8/300H, see @cite{H8/300H Series
-Programming Manual} (Hitachi).
-
-@code{@value{AS}} implements all the standard H8/300 opcodes. No additional
-pseudo-instructions are needed on this family.
-
-@ifset SMALL
-@c this table, due to the multi-col faking and hardcoded order, looks silly
-@c except in smallbook. See comments below "@set SMALL" near top of this file.
-
-The following table summarizes the H8/300 opcodes, and their arguments.
-Entries marked @samp{*} are opcodes used only on the H8/300H.
-
-@smallexample
-@c Using @group seems to use the normal baselineskip, not the smallexample
-@c baselineskip; looks approx doublespaced.
- @i{Legend:}
- Rs @r{source register}
- Rd @r{destination register}
- abs @r{absolute address}
- imm @r{immediate data}
- disp:N @r{N-bit displacement from a register}
- pcrel:N @r{N-bit displacement relative to program counter}
-
- add.b #imm,rd * andc #imm,ccr
- add.b rs,rd band #imm,rd
- add.w rs,rd band #imm,@@rd
-* add.w #imm,rd band #imm,@@abs:8
-* add.l rs,rd bra pcrel:8
-* add.l #imm,rd * bra pcrel:16
- adds #imm,rd bt pcrel:8
- addx #imm,rd * bt pcrel:16
- addx rs,rd brn pcrel:8
- and.b #imm,rd * brn pcrel:16
- and.b rs,rd bf pcrel:8
-* and.w rs,rd * bf pcrel:16
-* and.w #imm,rd bhi pcrel:8
-* and.l #imm,rd * bhi pcrel:16
-* and.l rs,rd bls pcrel:8
-@page
-* bls pcrel:16 bld #imm,rd
- bcc pcrel:8 bld #imm,@@rd
-* bcc pcrel:16 bld #imm,@@abs:8
- bhs pcrel:8 bnot #imm,rd
-* bhs pcrel:16 bnot #imm,@@rd
- bcs pcrel:8 bnot #imm,@@abs:8
-* bcs pcrel:16 bnot rs,rd
- blo pcrel:8 bnot rs,@@rd
-* blo pcrel:16 bnot rs,@@abs:8
- bne pcrel:8 bor #imm,rd
-* bne pcrel:16 bor #imm,@@rd
- beq pcrel:8 bor #imm,@@abs:8
-* beq pcrel:16 bset #imm,rd
- bvc pcrel:8 bset #imm,@@rd
-* bvc pcrel:16 bset #imm,@@abs:8
- bvs pcrel:8 bset rs,rd
-* bvs pcrel:16 bset rs,@@rd
- bpl pcrel:8 bset rs,@@abs:8
-* bpl pcrel:16 bsr pcrel:8
- bmi pcrel:8 bsr pcrel:16
-* bmi pcrel:16 bst #imm,rd
- bge pcrel:8 bst #imm,@@rd
-* bge pcrel:16 bst #imm,@@abs:8
- blt pcrel:8 btst #imm,rd
-* blt pcrel:16 btst #imm,@@rd
- bgt pcrel:8 btst #imm,@@abs:8
-* bgt pcrel:16 btst rs,rd
- ble pcrel:8 btst rs,@@rd
-* ble pcrel:16 btst rs,@@abs:8
- bclr #imm,rd bxor #imm,rd
- bclr #imm,@@rd bxor #imm,@@rd
- bclr #imm,@@abs:8 bxor #imm,@@abs:8
- bclr rs,rd cmp.b #imm,rd
- bclr rs,@@rd cmp.b rs,rd
- bclr rs,@@abs:8 cmp.w rs,rd
- biand #imm,rd cmp.w rs,rd
- biand #imm,@@rd * cmp.w #imm,rd
- biand #imm,@@abs:8 * cmp.l #imm,rd
- bild #imm,rd * cmp.l rs,rd
- bild #imm,@@rd daa rs
- bild #imm,@@abs:8 das rs
- bior #imm,rd dec.b rs
- bior #imm,@@rd * dec.w #imm,rd
- bior #imm,@@abs:8 * dec.l #imm,rd
- bist #imm,rd divxu.b rs,rd
- bist #imm,@@rd * divxu.w rs,rd
- bist #imm,@@abs:8 * divxs.b rs,rd
- bixor #imm,rd * divxs.w rs,rd
- bixor #imm,@@rd eepmov
- bixor #imm,@@abs:8 * eepmovw
-@page
-* exts.w rd mov.w rs,@@abs:16
-* exts.l rd * mov.l #imm,rd
-* extu.w rd * mov.l rs,rd
-* extu.l rd * mov.l @@rs,rd
- inc rs * mov.l @@(disp:16,rs),rd
-* inc.w #imm,rd * mov.l @@(disp:24,rs),rd
-* inc.l #imm,rd * mov.l @@rs+,rd
- jmp @@rs * mov.l @@abs:16,rd
- jmp abs * mov.l @@abs:24,rd
- jmp @@@@abs:8 * mov.l rs,@@rd
- jsr @@rs * mov.l rs,@@(disp:16,rd)
- jsr abs * mov.l rs,@@(disp:24,rd)
- jsr @@@@abs:8 * mov.l rs,@@-rd
- ldc #imm,ccr * mov.l rs,@@abs:16
- ldc rs,ccr * mov.l rs,@@abs:24
-* ldc @@abs:16,ccr movfpe @@abs:16,rd
-* ldc @@abs:24,ccr movtpe rs,@@abs:16
-* ldc @@(disp:16,rs),ccr mulxu.b rs,rd
-* ldc @@(disp:24,rs),ccr * mulxu.w rs,rd
-* ldc @@rs+,ccr * mulxs.b rs,rd
-* ldc @@rs,ccr * mulxs.w rs,rd
-* mov.b @@(disp:24,rs),rd neg.b rs
-* mov.b rs,@@(disp:24,rd) * neg.w rs
- mov.b @@abs:16,rd * neg.l rs
- mov.b rs,rd nop
- mov.b @@abs:8,rd not.b rs
- mov.b rs,@@abs:8 * not.w rs
- mov.b rs,rd * not.l rs
- mov.b #imm,rd or.b #imm,rd
- mov.b @@rs,rd or.b rs,rd
- mov.b @@(disp:16,rs),rd * or.w #imm,rd
- mov.b @@rs+,rd * or.w rs,rd
- mov.b @@abs:8,rd * or.l #imm,rd
- mov.b rs,@@rd * or.l rs,rd
- mov.b rs,@@(disp:16,rd) orc #imm,ccr
- mov.b rs,@@-rd pop.w rs
- mov.b rs,@@abs:8 * pop.l rs
- mov.w rs,@@rd push.w rs
-* mov.w @@(disp:24,rs),rd * push.l rs
-* mov.w rs,@@(disp:24,rd) rotl.b rs
-* mov.w @@abs:24,rd * rotl.w rs
-* mov.w rs,@@abs:24 * rotl.l rs
- mov.w rs,rd rotr.b rs
- mov.w #imm,rd * rotr.w rs
- mov.w @@rs,rd * rotr.l rs
- mov.w @@(disp:16,rs),rd rotxl.b rs
- mov.w @@rs+,rd * rotxl.w rs
- mov.w @@abs:16,rd * rotxl.l rs
- mov.w rs,@@(disp:16,rd) rotxr.b rs
- mov.w rs,@@-rd * rotxr.w rs
-@page
-* rotxr.l rs * stc ccr,@@(disp:24,rd)
- bpt * stc ccr,@@-rd
- rte * stc ccr,@@abs:16
- rts * stc ccr,@@abs:24
- shal.b rs sub.b rs,rd
-* shal.w rs sub.w rs,rd
-* shal.l rs * sub.w #imm,rd
- shar.b rs * sub.l rs,rd
-* shar.w rs * sub.l #imm,rd
-* shar.l rs subs #imm,rd
- shll.b rs subx #imm,rd
-* shll.w rs subx rs,rd
-* shll.l rs * trapa #imm
- shlr.b rs xor #imm,rd
-* shlr.w rs xor rs,rd
-* shlr.l rs * xor.w #imm,rd
- sleep * xor.w rs,rd
- stc ccr,rd * xor.l #imm,rd
-* stc ccr,@@rs * xor.l rs,rd
-* stc ccr,@@(disp:16,rd) xorc #imm,ccr
-@end smallexample
-@end ifset
-
-@cindex size suffixes, H8/300
-@cindex H8/300 size suffixes
-Four H8/300 instructions (@code{add}, @code{cmp}, @code{mov},
-@code{sub}) are defined with variants using the suffixes @samp{.b},
-@samp{.w}, and @samp{.l} to specify the size of a memory operand.
-@code{@value{AS}} supports these suffixes, but does not require them;
-since one of the operands is always a register, @code{@value{AS}} can
-deduce the correct size.
-
-For example, since @code{r0} refers to a 16-bit register,
-@example
-mov r0,@@foo
-@exdent is equivalent to
-mov.w r0,@@foo
-@end example
-
-If you use the size suffixes, @code{@value{AS}} issues a warning when
-the suffix and the register size do not match.
+@include c-h8300.texi
@end ifset
@ifset H8/500
-@page
-@node H8/500-Dependent
-@chapter H8/500 Dependent Features
-
-@cindex H8/500 support
-@menu
-* H8/500 Options:: Options
-* H8/500 Syntax:: Syntax
-* H8/500 Floating Point:: Floating Point
-* H8/500 Directives:: H8/500 Machine Directives
-* H8/500 Opcodes:: Opcodes
-@end menu
-
-@node H8/500 Options
-@section Options
-
-@cindex H8/500 options (none)
-@cindex options, H8/500 (none)
-@code{@value{AS}} has no additional command-line options for the Hitachi
-H8/500 family.
-
-@node H8/500 Syntax
-@section Syntax
-
-@menu
-* H8/500-Chars:: Special Characters
-* H8/500-Regs:: Register Names
-* H8/500-Addressing:: Addressing Modes
-@end menu
-
-@node H8/500-Chars
-@subsection Special Characters
-
-@cindex line comment character, H8/500
-@cindex H8/500 line comment character
-@samp{!} is the line comment character.
-
-@cindex line separator, H8/500
-@cindex statement separator, H8/500
-@cindex H8/500 line separator
-@samp{;} can be used instead of a newline to separate statements.
-
-@cindex symbol names, @samp{$} in
-@cindex @code{$} in symbol names
-Since @samp{$} has no special meaning, you may use it in symbol names.
-
-@node H8/500-Regs
-@subsection Register Names
-
-@cindex H8/500 registers
-@cindex registers, H8/500
-You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
-@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, and @samp{r7} to refer to
-the H8/500 registers.
-
-The H8/500 also has these control registers:
-
-@table @code
-@item cp
-code pointer
-
-@item dp
-data pointer
-
-@item bp
-base pointer
-
-@item tp
-stack top pointer
-
-@item ep
-extra pointer
-
-@item sr
-status register
-
-@item ccr
-condition code register
-@end table
-
-All registers are 16 bits long. To represent 32 bit numbers, use two
-adjacent registers; for distant memory addresses, use one of the segment
-pointers (@code{cp} for the program counter; @code{dp} for
-@code{r0}--@code{r3}; @code{ep} for @code{r4} and @code{r5}; and
-@code{tp} for @code{r6} and @code{r7}.
-
-@node H8/500-Addressing
-@subsection Addressing Modes
-
-@cindex addressing modes, H8/500
-@cindex H8/500 addressing modes
-@value{AS} understands the following addressing modes for the H8/500:
-@table @code
-@item R@var{n}
-Register direct
-
-@item @@R@var{n}
-Register indirect
-
-@item @@(d:8, R@var{n})
-Register indirect with 8 bit signed displacement
-
-@item @@(d:16, R@var{n})
-Register indirect with 16 bit signed displacement
-
-@item @@-R@var{n}
-Register indirect with pre-decrement
-
-@item @@R@var{n}+
-Register indirect with post-increment
-
-@item @@@var{aa}:8
-8 bit absolute address
-
-@item @@@var{aa}:16
-16 bit absolute address
-
-@item #@var{xx}:8
-8 bit immediate
-
-@item #@var{xx}:16
-16 bit immediate
-@end table
-
-@node H8/500 Floating Point
-@section Floating Point
-
-@cindex floating point, H8/500 (@sc{ieee})
-@cindex H8/500 floating point (@sc{ieee})
-The H8/500 family has no hardware floating point, but the @code{.float}
-directive generates @sc{ieee} floating-point numbers for compatibility
-with other development tools.
-
-@node H8/500 Directives
-@section H8/500 Machine Directives
-
-@cindex H8/500 machine directives (none)
-@cindex machine directives, H8/500 (none)
-@cindex @code{word} directive, H8/500
-@cindex @code{int} directive, H8/500
-@code{@value{AS}} has no machine-dependent directives for the H8/500.
-However, on this platform the @samp{.int} and @samp{.word} directives
-generate 16-bit numbers.
-
-@node H8/500 Opcodes
-@section Opcodes
-
-@cindex H8/500 opcode summary
-@cindex opcode summary, H8/500
-@cindex mnemonics, H8/500
-@cindex instruction summary, H8/500
-For detailed information on the H8/500 machine instruction set, see
-@cite{H8/500 Series Programming Manual} (Hitachi M21T001).
-
-@code{@value{AS}} implements all the standard H8/500 opcodes. No additional
-pseudo-instructions are needed on this family.
-
-@ifset SMALL
-@c this table, due to the multi-col faking and hardcoded order, looks silly
-@c except in smallbook. See comments below "@set SMALL" near top of this file.
-
-The following table summarizes H8/500 opcodes and their operands:
-
-@c Use @group if it ever works, instead of @page
-@page
-@smallexample
-@i{Legend:}
-abs8 @r{8-bit absolute address}
-abs16 @r{16-bit absolute address}
-abs24 @r{24-bit absolute address}
-crb @r{@code{ccr}, @code{br}, @code{ep}, @code{dp}, @code{tp}, @code{dp}}
-disp8 @r{8-bit displacement}
-ea @r{@code{rn}, @code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},}
- @r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16},}
- @r{@code{#xx:8}, @code{#xx:16}}
-ea_mem @r{@code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},}
- @r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16}}
-ea_noimm @r{@code{rn}, @code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},}
- @r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16}}
-fp r6
-imm4 @r{4-bit immediate data}
-imm8 @r{8-bit immediate data}
-imm16 @r{16-bit immediate data}
-pcrel8 @r{8-bit offset from program counter}
-pcrel16 @r{16-bit offset from program counter}
-qim @r{@code{-2}, @code{-1}, @code{1}, @code{2}}
-rd @r{any register}
-rs @r{a register distinct from rd}
-rlist @r{comma-separated list of registers in parentheses;}
- @r{register ranges @code{rd-rs} are allowed}
-sp @r{stack pointer (@code{r7})}
-sr @r{status register}
-sz @r{size; @samp{.b} or @samp{.w}. If omitted, default @samp{.w}}
-
-ldc[.b] ea,crb bcc[.w] pcrel16
-ldc[.w] ea,sr bcc[.b] pcrel8
-add[:q] sz qim,ea_noimm bhs[.w] pcrel16
-add[:g] sz ea,rd bhs[.b] pcrel8
-adds sz ea,rd bcs[.w] pcrel16
-addx sz ea,rd bcs[.b] pcrel8
-and sz ea,rd blo[.w] pcrel16
-andc[.b] imm8,crb blo[.b] pcrel8
-andc[.w] imm16,sr bne[.w] pcrel16
-bpt bne[.b] pcrel8
-bra[.w] pcrel16 beq[.w] pcrel16
-bra[.b] pcrel8 beq[.b] pcrel8
-bt[.w] pcrel16 bvc[.w] pcrel16
-bt[.b] pcrel8 bvc[.b] pcrel8
-brn[.w] pcrel16 bvs[.w] pcrel16
-brn[.b] pcrel8 bvs[.b] pcrel8
-bf[.w] pcrel16 bpl[.w] pcrel16
-bf[.b] pcrel8 bpl[.b] pcrel8
-bhi[.w] pcrel16 bmi[.w] pcrel16
-bhi[.b] pcrel8 bmi[.b] pcrel8
-bls[.w] pcrel16 bge[.w] pcrel16
-bls[.b] pcrel8 bge[.b] pcrel8
-@page
-blt[.w] pcrel16 mov[:g][.b] imm8,ea_mem
-blt[.b] pcrel8 mov[:g][.w] imm16,ea_mem
-bgt[.w] pcrel16 movfpe[.b] ea,rd
-bgt[.b] pcrel8 movtpe[.b] rs,ea_noimm
-ble[.w] pcrel16 mulxu sz ea,rd
-ble[.b] pcrel8 neg sz ea
-bclr sz imm4,ea_noimm nop
-bclr sz rs,ea_noimm not sz ea
-bnot sz imm4,ea_noimm or sz ea,rd
-bnot sz rs,ea_noimm orc[.b] imm8,crb
-bset sz imm4,ea_noimm orc[.w] imm16,sr
-bset sz rs,ea_noimm pjmp abs24
-bsr[.b] pcrel8 pjmp @@rd
-bsr[.w] pcrel16 pjsr abs24
-btst sz imm4,ea_noimm pjsr @@rd
-btst sz rs,ea_noimm prtd imm8
-clr sz ea prtd imm16
-cmp[:e][.b] imm8,rd prts
-cmp[:i][.w] imm16,rd rotl sz ea
-cmp[:g].b imm8,ea_noimm rotr sz ea
-cmp[:g][.w] imm16,ea_noimm rotxl sz ea
-Cmp[:g] sz ea,rd rotxr sz ea
-dadd rs,rd rtd imm8
-divxu sz ea,rd rtd imm16
-dsub rs,rd rts
-exts[.b] rd scb/f rs,pcrel8
-extu[.b] rd scb/ne rs,pcrel8
-jmp @@rd scb/eq rs,pcrel8
-jmp @@(imm8,rd) shal sz ea
-jmp @@(imm16,rd) shar sz ea
-jmp abs16 shll sz ea
-jsr @@rd shlr sz ea
-jsr @@(imm8,rd) sleep
-jsr @@(imm16,rd) stc[.b] crb,ea_noimm
-jsr abs16 stc[.w] sr,ea_noimm
-ldm @@sp+,(rlist) stm (rlist),@@-sp
-link fp,imm8 sub sz ea,rd
-link fp,imm16 subs sz ea,rd
-mov[:e][.b] imm8,rd subx sz ea,rd
-mov[:i][.w] imm16,rd swap[.b] rd
-mov[:l][.w] abs8,rd tas[.b] ea
-mov[:l].b abs8,rd trapa imm4
-mov[:s][.w] rs,abs8 trap/vs
-mov[:s].b rs,abs8 tst sz ea
-mov[:f][.w] @@(disp8,fp),rd unlk fp
-mov[:f][.w] rs,@@(disp8,fp) xch[.w] rs,rd
-mov[:f].b @@(disp8,fp),rd xor sz ea,rd
-mov[:f].b rs,@@(disp8,fp) xorc.b imm8,crb
-mov[:g] sz rs,ea_mem xorc.w imm16,sr
-mov[:g] sz ea,rd
-@end smallexample
-@end ifset
+@include c-h8500.texi
@end ifset
@ifset HPPA
-@page
-@node HPPA-Dependent
-@chapter HPPA Dependent Features
-
-@cindex support
-@menu
-* HPPA Notes:: Notes
-* HPPA Options:: Options
-* HPPA Syntax:: Syntax
-* HPPA Floating Point:: Floating Point
-* HPPA Directives:: HPPA Machine Directives
-* HPPA Opcodes:: Opcodes
-@end menu
-
-@node HPPA Notes
-@section Notes
-As a back end for @sc{gnu} @sc{cc} @code{@value{AS}} has been throughly tested and should
-work extremely well. We have tested it only minimally on hand written assembly
-code and no one has tested it much on the assembly output from the HP
-compilers.
-
-The format of the debugging sections has changed since the original
-@code{@value{AS}} port (version 1.3X) was released; therefore,
-you must rebuild all HPPA objects and libraries with the new
-assembler so that you can debug the final executable.
-
-The HPPA @code{@value{AS}} port generates a small subset of the relocations
-available in the SOM and ELF object file formats. Additional relocation
-support will be added as it becomes necessary.
-
-@node HPPA Options
-@section Options
-@code{@value{AS}} has no machine-dependent command-line options for the HPPA.
-
-@cindex HPPA Syntax
-@node HPPA Syntax
-@section Syntax
-The assembler syntax closely follows the HPPA instruction set
-reference manual; assembler directives and general syntax closely follow the
-HPPA assembly language reference manual, with a few noteworthy differences.
-
-First, a colon may immediately follow a label definition. This is
-simply for compatibility with how most assembly language programmers
-write code.
-
-Some obscure expression parsing problems may affect hand written code which
-uses the @code{spop} instructions, or code which makes significant
-use of the @code{!} line separator.
-
-@code{@value{AS}} is much less forgiving about missing arguments and other
-similar oversights than the HP assembler. @code{@value{AS}} notifies you
-of missing arguments as syntax errors; this is regarded as a feature, not a
-bug.
-
-Finally, @code{@value{AS}} allows you to use an external symbol without
-explicitly importing the symbol. @emph{Warning:} in the future this will be
-an error for HPPA targets.
-
-Special characters for HPPA targets include:
-
-@samp{;} is the line comment character.
-
-@samp{!} can be used instead of a newline to separate statements.
-
-Since @samp{$} has no special meaning, you may use it in symbol names.
-
-@node HPPA Floating Point
-@section Floating Point
-@cindex floating point, HPPA (@sc{ieee})
-@cindex HPPA floating point (@sc{ieee})
-The HPPA family uses @sc{ieee} floating-point numbers.
-
-@node HPPA Directives
-@section HPPA Assembler Directives
-
-@code{@value{AS}} for the HPPA supports many additional directives for
-compatibility with the native assembler. This section describes them only
-briefly. For detailed information on HPPA-specific assembler directives, see
-@cite{HP9000 Series 800 Assembly Language Reference Manual} (HP 92432-90001).
-
-@cindex HPPA directives not supported
-@code{@value{AS}} does @emph{not} support the following assembler directives
-described in the HP manual:
-
-@example
-.endm .liston
-.enter .locct
-.leave .macro
-.listoff
-@end example
-
-@cindex @code{.param} on HPPA
-Beyond those implemented for compatibility, @code{@value{AS}} supports one
-additional assembler directive for the HPPA: @code{.param}. It conveys
-register argument locations for static functions. Its syntax closely follows
-the @code{.export} directive.
-
-@cindex HPPA-only directives
-These are the additional directives in @code{@value{AS}} for the HPPA:
-
-@table @code
-@item .block @var{n}
-@itemx .blockz @var{n}
-Reserve @var{n} bytes of storage, and initialize them to zero.
-
-@item .call
-Mark the beginning of a procedure call. Only the special case with @emph{no
-arguments} is allowed.
-
-@item .callinfo [ @var{param}=@var{value}, @dots{} ] [ @var{flag}, @dots{} ]
-Specify a number of parameters and flags that define the environment for a
-procedure.
-
-@var{param} may be any of @samp{frame} (frame size), @samp{entry_gr} (end of
-general register range), @samp{entry_fr} (end of float register range),
-@samp{entry_sr} (end of space register range).
-
-The values for @var{flag} are @samp{calls} or @samp{caller} (proc has
-subroutines), @samp{no_calls} (proc does not call subroutines), @samp{save_rp}
-(preserve return pointer), @samp{save_sp} (proc preserves stack pointer),
-@samp{no_unwind} (do not unwind this proc), @samp{hpux_int} (proc is interrupt
-routine).
-
-@item .code
-Assemble into the standard section called @samp{$TEXT$}, subsection
-@samp{$CODE$}.
-
-@ifset SOM
-@item .copyright "@var{string}"
-In the SOM object format, insert @var{string} into the object code, marked as a
-copyright string.
-@end ifset
-
-@ifset ELF
-@item .copyright "@var{string}"
-In the ELF object format, insert @var{string} into the object code, marked as a
-version string.
-@end ifset
-
-@item .enter
-Not yet supported; the assembler rejects programs containing this directive.
-
-@item .entry
-Mark the beginning of a procedure.
-
-@item .exit
-Mark the end of a procedure.
-
-@item .export @var{name} [ ,@var{typ} ] [ ,@var{param}=@var{r} ]
-Make a procedure @var{name} available to callers. @var{typ}, if present, must
-be one of @samp{absolute}, @samp{code} (ELF only, not SOM), @samp{data},
-@samp{entry}, @samp{data}, @samp{entry}, @samp{millicode}, @samp{plabel},
-@samp{pri_prog}, or @samp{sec_prog}.
-
-@var{param}, if present, provides either relocation information for the
-procedure arguments and result, or a privilege level. @var{param} may be
-@samp{argw@var{n}} (where @var{n} ranges from @code{0} to @code{3}, and
-indicates one of four one-word arguments); @samp{rtnval} (the procedure's
-result); or @samp{priv_lev} (privilege level). For arguments or the result,
-@var{r} specifies how to relocate, and must be one of @samp{no} (not
-relocatable), @samp{gr} (argument is in general register), @samp{fr} (in
-floating point register), or @samp{fu} (upper half of float register).
-For @samp{priv_lev}, @var{r} is an integer.
-
-@item .half @var{n}
-Define a two-byte integer constant @var{n}; synonym for the portable
-@code{@value{AS}} directive @code{.short}.
-
-@item .import @var{name} [ ,@var{typ} ]
-Converse of @code{.export}; make a procedure available to call. The arguments
-use the same conventions as the first two arguments for @code{.export}.
-
-@item .label @var{name}
-Define @var{name} as a label for the current assembly location.
-
-@item .leave
-Not yet supported; the assembler rejects programs containing this directive.
-
-@item .origin @var{lc}
-Advance location counter to @var{lc}. Synonym for the @code{@value{as}}
-portable directive @code{.org}.
-
-@item .param @var{name} [ ,@var{typ} ] [ ,@var{param}=@var{r} ]
-@c Not in HP manual; GNU HPPA extension
-Similar to @code{.export}, but used for static procedures.
-
-@item .proc
-Use preceding the first statement of a procedure.
-
-@item .procend
-Use following the last statement of a procedure.
-
-@item @var{label} .reg @var{expr}
-@c ?? Not in HP manual (Jan 1988 vn)
-Synonym for @code{.equ}; define @var{label} with the absolute expression
-@var{expr} as its value.
-
-@item .space @var{secname} [ ,@var{params} ]
-Switch to section @var{secname}, creating a new section by that name if
-necessary. You may only use @var{params} when creating a new section, not
-when switching to an existing one. @var{secname} may identify a section by
-number rather than by name.
-
-If specified, the list @var{params} declares attributes of the section,
-identified by keywords. The keywords recognized are @samp{spnum=@var{exp}}
-(identify this section by the number @var{exp}, an absolute expression),
-@samp{sort=@var{exp}} (order sections according to this sort key when linking;
-@var{exp} is an absolute expression), @samp{unloadable} (section contains no
-loadable data), @samp{notdefined} (this section defined elsewhere), and
-@samp{private} (data in this section not available to other programs).
-
-@item .spnum @var{secnam}
-@c ?? Not in HP manual (Jan 1988)
-Allocate four bytes of storage, and initialize them with the section number of
-the section named @var{secnam}. (You can define the section number with the
-HPPA @code{.space} directive.)
-
-@item .string "@var{str}"
-@cindex @code{string} directive on HPPA
-Copy the characters in the string @var{str} to the object file.
-@xref{Strings,,Strings}, for information on escape sequences you can use in
-@code{@value{AS}} strings.
-
-@emph{Warning!} The HPPA version of @code{.string} differs from the
-usual @code{@value{AS}} definition: it does @emph{not} write a zero byte
-after copying @var{str}.
-
-@item .stringz "@var{str}"
-Like @code{.string}, but appends a zero byte after copying @var{str} to object
-file.
-
-@item .subspa @var{name} [ ,@var{params} ]
-Similar to @code{.space}, but selects a subsection @var{name} within the
-current section. You may only specify @var{params} when you create a
-subsection (in the first instance of @code{.subspa} for this @var{name}).
-
-If specified, the list @var{params} declares attributes of the subsection,
-identified by keywords. The keywords recognized are @samp{quad=@var{expr}}
-(``quadrant'' for this subsection), @samp{align=@var{expr}} (alignment for
-beginning of this subsection; a power of two), @samp{access=@var{expr}} (value
-for ``access rights'' field), @samp{sort=@var{expr}} (sorting order for this
-subspace in link), @samp{code_only} (subsection contains only code),
-@samp{unloadable} (subsection cannot be loaded into memory), @samp{common}
-(subsection is common block), @samp{dup_comm} (initialized data may have
-duplicate names), or @samp{zero} (subsection is all zeros, do not write in
-object file).
-
-@item .version "@var{str}"
-Write @var{str} as version identifier in object code.
-@end table
-
-@node HPPA Opcodes
-@section Opcodes
-For detailed information on the HPPA machine instruction set, see
-@cite{PA-RISC Architecture and Instruction Set Reference Manual}
-(HP 09740-90039).
+@include c-hppa.texi
@end ifset
@ifset SH
-@page
-@node SH-Dependent
-@chapter Hitachi SH Dependent Features
-
-@cindex SH support
-@menu
-* SH Options:: Options
-* SH Syntax:: Syntax
-* SH Floating Point:: Floating Point
-* SH Directives:: SH Machine Directives
-* SH Opcodes:: Opcodes
-@end menu
-
-@node SH Options
-@section Options
-
-@cindex SH options (none)
-@cindex options, SH (none)
-@code{@value{AS}} has no additional command-line options for the Hitachi
-SH family.
-
-@node SH Syntax
-@section Syntax
-
-@menu
-* SH-Chars:: Special Characters
-* SH-Regs:: Register Names
-* SH-Addressing:: Addressing Modes
-@end menu
-
-@node SH-Chars
-@subsection Special Characters
-
-@cindex line comment character, SH
-@cindex SH line comment character
-@samp{!} is the line comment character.
-
-@cindex line separator, SH
-@cindex statement separator, SH
-@cindex SH line separator
-You can use @samp{;} instead of a newline to separate statements.
-
-@cindex symbol names, @samp{$} in
-@cindex @code{$} in symbol names
-Since @samp{$} has no special meaning, you may use it in symbol names.
-
-@node SH-Regs
-@subsection Register Names
-
-@cindex SH registers
-@cindex registers, SH
-You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
-@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
-@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
-and @samp{r15} to refer to the SH registers.
-
-The SH also has these control registers:
-
-@table @code
-@item pr
-procedure register (holds return address)
-
-@item pc
-program counter
-
-@item mach
-@itemx macl
-high and low multiply accumulator registers
-
-@item sr
-status register
-
-@item gbr
-global base register
-
-@item vbr
-vector base register (for interrupt vectors)
-@end table
-
-@node SH-Addressing
-@subsection Addressing Modes
-
-@cindex addressing modes, SH
-@cindex SH addressing modes
-@code{@value{AS}} understands the following addressing modes for the SH.
-@code{R@var{n}} in the following refers to any of the numbered
-registers, but @emph{not} the control registers.
-
-@table @code
-@item R@var{n}
-Register direct
-
-@item @@R@var{n}
-Register indirect
-
-@item @@-R@var{n}
-Register indirect with pre-decrement
-
-@item @@R@var{n}+
-Register indirect with post-increment
-
-@item @@(@var{disp}, R@var{n})
-Register indirect with displacement
-
-@item @@(R0, R@var{n})
-Register indexed
-
-@item @@(@var{disp}, GBR)
-@code{GBR} offset
-
-@item @@(R0, GBR)
-GBR indexed
-
-@item @var{addr}
-@itemx @@(@var{disp}, PC)
-PC relative address (for branch or for addressing memory). The
-@code{@value{AS}} implementation allows you to use the simpler form
-@var{addr} anywhere a PC relative address is called for; the alternate
-form is supported for compatibility with other assemblers.
-
-@item #@var{imm}
-Immediate data
-@end table
-
-@node SH Floating Point
-@section Floating Point
-
-@cindex floating point, SH (@sc{ieee})
-@cindex SH floating point (@sc{ieee})
-The SH family has no hardware floating point, but the @code{.float}
-directive generates @sc{ieee} floating-point numbers for compatibility
-with other development tools.
-
-@node SH Directives
-@section SH Machine Directives
-
-@cindex SH machine directives (none)
-@cindex machine directives, SH (none)
-@cindex @code{word} directive, SH
-@cindex @code{int} directive, SH
-@code{@value{AS}} has no machine-dependent directives for the SH.
-
-@node SH Opcodes
-@section Opcodes
-
-@cindex SH opcode summary
-@cindex opcode summary, SH
-@cindex mnemonics, SH
-@cindex instruction summary, SH
-For detailed information on the SH machine instruction set, see
-@cite{SH-Microcomputer User's Manual} (Hitachi Micro Systems, Inc.).
-
-@code{@value{AS}} implements all the standard SH opcodes. No additional
-pseudo-instructions are needed on this family. Note, however, that
-because @code{@value{AS}} supports a simpler form of PC-relative
-addressing, you may simply write (for example)
-
-@example
-mov.l bar,r0
-@end example
-
-@noindent
-where other assemblers might require an explicit displacement to
-@code{bar} from the program counter:
-
-@example
-mov.l @@(@var{disp}, PC)
-@end example
-
-@ifset SMALL
-@c this table, due to the multi-col faking and hardcoded order, looks silly
-@c except in smallbook. See comments below "@set SMALL" near top of this file.
-
-Here is a summary of SH opcodes:
-
-@page
-@smallexample
-@i{Legend:}
-Rn @r{a numbered register}
-Rm @r{another numbered register}
-#imm @r{immediate data}
-disp @r{displacement}
-disp8 @r{8-bit displacement}
-disp12 @r{12-bit displacement}
-
-add #imm,Rn lds.l @@Rn+,PR
-add Rm,Rn mac.w @@Rm+,@@Rn+
-addc Rm,Rn mov #imm,Rn
-addv Rm,Rn mov Rm,Rn
-and #imm,R0 mov.b Rm,@@(R0,Rn)
-and Rm,Rn mov.b Rm,@@-Rn
-and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
-bf disp8 mov.b @@(disp,Rm),R0
-bra disp12 mov.b @@(disp,GBR),R0
-bsr disp12 mov.b @@(R0,Rm),Rn
-bt disp8 mov.b @@Rm+,Rn
-clrmac mov.b @@Rm,Rn
-clrt mov.b R0,@@(disp,Rm)
-cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
-cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn)
-cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
-cmp/gt Rm,Rn mov.l Rm,@@-Rn
-cmp/hi Rm,Rn mov.l Rm,@@Rn
-cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm
-cmp/pl Rn mov.l @@(disp,GBR),R0
-cmp/pz Rn mov.l @@(disp,PC),Rn
-cmp/str Rm,Rn mov.l @@(R0,Rm),Rn
-div0s Rm,Rn mov.l @@Rm+,Rn
-div0u mov.l @@Rm,Rn
-div1 Rm,Rn mov.l R0,@@(disp,GBR)
-exts.b Rm,Rn mov.w Rm,@@(R0,Rn)
-exts.w Rm,Rn mov.w Rm,@@-Rn
-extu.b Rm,Rn mov.w Rm,@@Rn
-extu.w Rm,Rn mov.w @@(disp,Rm),R0
-jmp @@Rn mov.w @@(disp,GBR),R0
-jsr @@Rn mov.w @@(disp,PC),Rn
-ldc Rn,GBR mov.w @@(R0,Rm),Rn
-ldc Rn,SR mov.w @@Rm+,Rn
-ldc Rn,VBR mov.w @@Rm,Rn
-ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm)
-ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
-ldc.l @@Rn+,VBR mova @@(disp,PC),R0
-lds Rn,MACH movt Rn
-lds Rn,MACL muls Rm,Rn
-lds Rn,PR mulu Rm,Rn
-lds.l @@Rn+,MACH neg Rm,Rn
-lds.l @@Rn+,MACL negc Rm,Rn
-@page
-nop stc VBR,Rn
-not Rm,Rn stc.l GBR,@@-Rn
-or #imm,R0 stc.l SR,@@-Rn
-or Rm,Rn stc.l VBR,@@-Rn
-or.b #imm,@@(R0,GBR) sts MACH,Rn
-rotcl Rn sts MACL,Rn
-rotcr Rn sts PR,Rn
-rotl Rn sts.l MACH,@@-Rn
-rotr Rn sts.l MACL,@@-Rn
-rte sts.l PR,@@-Rn
-rts sub Rm,Rn
-sett subc Rm,Rn
-shal Rn subv Rm,Rn
-shar Rn swap.b Rm,Rn
-shll Rn swap.w Rm,Rn
-shll16 Rn tas.b @@Rn
-shll2 Rn trapa #imm
-shll8 Rn tst #imm,R0
-shlr Rn tst Rm,Rn
-shlr16 Rn tst.b #imm,@@(R0,GBR)
-shlr2 Rn xor #imm,R0
-shlr8 Rn xor Rm,Rn
-sleep xor.b #imm,@@(R0,GBR)
-stc GBR,Rn xtrct Rm,Rn
-stc SR,Rn
-@end smallexample
-@end ifset
-
-@ifset Hitachi-all
-@ifclear GENERIC
-@raisesections
-@end ifclear
+@include c-sh.texi
@end ifset
-@end ifset
@ifset I960
-@ifset GENERIC
-@page
-@node i960-Dependent
-@chapter Intel 80960 Dependent Features
-@end ifset
-@ifclear GENERIC
-@node Machine Dependencies
-@chapter Intel 80960 Dependent Features
-@end ifclear
-
-@cindex i960 support
-@menu
-* Options-i960:: i960 Command-line Options
-* Floating Point-i960:: Floating Point
-* Directives-i960:: i960 Machine Directives
-* Opcodes for i960:: i960 Opcodes
-@end menu
-
-@c FIXME! Add Syntax sec with discussion of bitfields here, at least so
-@c long as they're not turned on for other machines than 960.
-
-@node Options-i960
-
-@section i960 Command-line Options
-
-@cindex i960 options
-@cindex options, i960
-@table @code
-
-@item -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC
-@cindex i960 architecture options
-@cindex architecture options, i960
-@cindex @code{-A} options, i960
-Select the 80960 architecture. Instructions or features not supported
-by the selected architecture cause fatal errors.
-
-@samp{-ACA} is equivalent to @samp{-ACA_A}; @samp{-AKC} is equivalent to
-@samp{-AMC}. Synonyms are provided for compatibility with other tools.
-
-If you do not specify any of these options, @code{@value{AS}} generates code
-for any instruction or feature that is supported by @emph{some} version of the
-960 (even if this means mixing architectures!). In principle,
-@code{@value{AS}} attempts to deduce the minimal sufficient processor type if
-none is specified; depending on the object code format, the processor type may
-be recorded in the object file. If it is critical that the @code{@value{AS}}
-output match a specific architecture, specify that architecture explicitly.
-
-@item -b
-@cindex @code{-b} option, i960
-@cindex branch recording, i960
-@cindex i960 branch recording
-Add code to collect information about conditional branches taken, for
-later optimization using branch prediction bits. (The conditional branch
-instructions have branch prediction bits in the CA, CB, and CC
-architectures.) If @var{BR} represents a conditional branch instruction,
-the following represents the code generated by the assembler when
-@samp{-b} is specified:
-
-@smallexample
- call @var{increment routine}
- .word 0 # pre-counter
-Label: @var{BR}
- call @var{increment routine}
- .word 0 # post-counter
-@end smallexample
-
-The counter following a branch records the number of times that branch
-was @emph{not} taken; the differenc between the two counters is the
-number of times the branch @emph{was} taken.
-
-@cindex @code{gbr960}, i960 postprocessor
-@cindex branch statistics table, i960
-A table of every such @code{Label} is also generated, so that the
-external postprocessor @code{gbr960} (supplied by Intel) can locate all
-the counters. This table is always labelled @samp{__BRANCH_TABLE__};
-this is a local symbol to permit collecting statistics for many separate
-object files. The table is word aligned, and begins with a two-word
-header. The first word, initialized to 0, is used in maintaining linked
-lists of branch tables. The second word is a count of the number of
-entries in the table, which follow immediately: each is a word, pointing
-to one of the labels illustrated above.
-
-@c TEXI2ROFF-KILL
-@ifinfo
-@c END TEXI2ROFF-KILL
-@example
- +------------+------------+------------+ ... +------------+
- | | | | | |
- | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N |
- | | | | | |
- +------------+------------+------------+ ... +------------+
-
- __BRANCH_TABLE__ layout
-@end example
-@c TEXI2ROFF-KILL
-@end ifinfo
-@need 2000
-@tex
-\vskip 1pc
-\line{\leftskip=0pt\hskip\tableindent
-\boxit{2cm}{\tt *NEXT}\boxit{2cm}{\tt COUNT: \it N}\boxit{2cm}{\tt
-*BRLAB 1}\ibox{1cm}{\quad\dots}\boxit{2cm}{\tt *BRLAB \it N}\hfil}
-\centerline{\it {\tt \_\_BRANCH\_TABLE\_\_} layout}
-@end tex
-@c END TEXI2ROFF-KILL
-
-The first word of the header is used to locate multiple branch tables,
-since each object file may contain one. Normally the links are
-maintained with a call to an initialization routine, placed at the
-beginning of each function in the file. The @sc{gnu} C compiler
-generates these calls automatically when you give it a @samp{-b} option.
-For further details, see the documentation of @samp{gbr960}.
-
-@item -no-relax
-@cindex @code{-no-relax} option, i960
-Normally, Compare-and-Branch instructions with targets that require
-displacements greater than 13 bits (or that have external targets) are
-replaced with the corresponding compare (or @samp{chkbit}) and branch
-instructions. You can use the @samp{-no-relax} option to specify that
-@code{@value{AS}} should generate errors instead, if the target displacement
-is larger than 13 bits.
-
-This option does not affect the Compare-and-Jump instructions; the code
-emitted for them is @emph{always} adjusted when necessary (depending on
-displacement size), regardless of whether you use @samp{-no-relax}.
-@end table
-
-@node Floating Point-i960
-@section Floating Point
-
-@cindex floating point, i960 (@sc{ieee})
-@cindex i960 floating point (@sc{ieee})
-@code{@value{AS}} generates @sc{ieee} floating-point numbers for the directives
-@samp{.float}, @samp{.double}, @samp{.extended}, and @samp{.single}.
-
-@node Directives-i960
-@section i960 Machine Directives
-
-@cindex machine directives, i960
-@cindex i960 machine directives
-
-@table @code
-@cindex @code{bss} directive, i960
-@item .bss @var{symbol}, @var{length}, @var{align}
-Reserve @var{length} bytes in the bss section for a local @var{symbol},
-aligned to the power of two specified by @var{align}. @var{length} and
-@var{align} must be positive absolute expressions. This directive
-differs from @samp{.lcomm} only in that it permits you to specify
-an alignment. @xref{Lcomm,,@code{.lcomm}}.
-@end table
-
-@table @code
-@item .extended @var{flonums}
-@cindex @code{extended} directive, i960
-@code{.extended} expects zero or more flonums, separated by commas; for
-each flonum, @samp{.extended} emits an @sc{ieee} extended-format (80-bit)
-floating-point number.
-
-@item .leafproc @var{call-lab}, @var{bal-lab}
-@cindex @code{leafproc} directive, i960
-You can use the @samp{.leafproc} directive in conjunction with the
-optimized @code{callj} instruction to enable faster calls of leaf
-procedures. If a procedure is known to call no other procedures, you
-may define an entry point that skips procedure prolog code (and that does
-not depend on system-supplied saved context), and declare it as the
-@var{bal-lab} using @samp{.leafproc}. If the procedure also has an
-entry point that goes through the normal prolog, you can specify that
-entry point as @var{call-lab}.
-
-A @samp{.leafproc} declaration is meant for use in conjunction with the
-optimized call instruction @samp{callj}; the directive records the data
-needed later to choose between converting the @samp{callj} into a
-@code{bal} or a @code{call}.
-
-@var{call-lab} is optional; if only one argument is present, or if the
-two arguments are identical, the single argument is assumed to be the
-@code{bal} entry point.
-
-@item .sysproc @var{name}, @var{index}
-@cindex @code{sysproc} directive, i960
-The @samp{.sysproc} directive defines a name for a system procedure.
-After you define it using @samp{.sysproc}, you can use @var{name} to
-refer to the system procedure identified by @var{index} when calling
-procedures with the optimized call instruction @samp{callj}.
-
-Both arguments are required; @var{index} must be between 0 and 31
-(inclusive).
-@end table
-
-@node Opcodes for i960
-@section i960 Opcodes
-
-@cindex opcodes, i960
-@cindex i960 opcodes
-All Intel 960 machine instructions are supported;
-@pxref{Options-i960,,i960 Command-line Options} for a discussion of
-selecting the instruction subset for a particular 960
-architecture.@refill
-
-Some opcodes are processed beyond simply emitting a single corresponding
-instruction: @samp{callj}, and Compare-and-Branch or Compare-and-Jump
-instructions with target displacements larger than 13 bits.
-
-@menu
-* callj-i960:: @code{callj}
-* Compare-and-branch-i960:: Compare-and-Branch
-@end menu
-
-@node callj-i960
-@subsection @code{callj}
-
-@cindex @code{callj}, i960 pseudo-opcode
-@cindex i960 @code{callj} pseudo-opcode
-You can write @code{callj} to have the assembler or the linker determine
-the most appropriate form of subroutine call: @samp{call},
-@samp{bal}, or @samp{calls}. If the assembly source contains
-enough information---a @samp{.leafproc} or @samp{.sysproc} directive
-defining the operand---then @code{@value{AS}} translates the
-@code{callj}; if not, it simply emits the @code{callj}, leaving it
-for the linker to resolve.
-
-@node Compare-and-branch-i960
-@subsection Compare-and-Branch
-
-@cindex i960 compare/branch instructions
-@cindex compare/branch instructions, i960
-The 960 architectures provide combined Compare-and-Branch instructions
-that permit you to store the branch target in the lower 13 bits of the
-instruction word itself. However, if you specify a branch target far
-enough away that its address won't fit in 13 bits, the assembler can
-either issue an error, or convert your Compare-and-Branch instruction
-into separate instructions to do the compare and the branch.
-
-@cindex compare and jump expansions, i960
-@cindex i960 compare and jump expansions
-Whether @code{@value{AS}} gives an error or expands the instruction depends
-on two choices you can make: whether you use the @samp{-no-relax} option,
-and whether you use a ``Compare and Branch'' instruction or a ``Compare
-and Jump'' instruction. The ``Jump'' instructions are @emph{always}
-expanded if necessary; the ``Branch'' instructions are expanded when
-necessary @emph{unless} you specify @code{-no-relax}---in which case
-@code{@value{AS}} gives an error instead.
-
-These are the Compare-and-Branch instructions, their ``Jump'' variants,
-and the instruction pairs they may expand into:
-
-@c TEXI2ROFF-KILL
-@ifinfo
-@c END TEXI2ROFF-KILL
-@example
- Compare and
- Branch Jump Expanded to
- ------ ------ ------------
- bbc chkbit; bno
- bbs chkbit; bo
- cmpibe cmpije cmpi; be
- cmpibg cmpijg cmpi; bg
- cmpibge cmpijge cmpi; bge
- cmpibl cmpijl cmpi; bl
- cmpible cmpijle cmpi; ble
- cmpibno cmpijno cmpi; bno
- cmpibne cmpijne cmpi; bne
- cmpibo cmpijo cmpi; bo
- cmpobe cmpoje cmpo; be
- cmpobg cmpojg cmpo; bg
- cmpobge cmpojge cmpo; bge
- cmpobl cmpojl cmpo; bl
- cmpoble cmpojle cmpo; ble
- cmpobne cmpojne cmpo; bne
-@end example
-@c TEXI2ROFF-KILL
-@end ifinfo
-@tex
-\hskip\tableindent
-\halign{\hfil {\tt #}\quad&\hfil {\tt #}\qquad&{\tt #}\hfil\cr
-\omit{\hfil\it Compare and\hfil}\span\omit&\cr
-{\it Branch}&{\it Jump}&{\it Expanded to}\cr
- bbc& & chkbit; bno\cr
- bbs& & chkbit; bo\cr
- cmpibe& cmpije& cmpi; be\cr
- cmpibg& cmpijg& cmpi; bg\cr
- cmpibge& cmpijge& cmpi; bge\cr
- cmpibl& cmpijl& cmpi; bl\cr
- cmpible& cmpijle& cmpi; ble\cr
- cmpibno& cmpijno& cmpi; bno\cr
- cmpibne& cmpijne& cmpi; bne\cr
- cmpibo& cmpijo& cmpi; bo\cr
- cmpobe& cmpoje& cmpo; be\cr
- cmpobg& cmpojg& cmpo; bg\cr
- cmpobge& cmpojge& cmpo; bge\cr
- cmpobl& cmpojl& cmpo; bl\cr
- cmpoble& cmpojle& cmpo; ble\cr
- cmpobne& cmpojne& cmpo; bne\cr}
-@end tex
-@c END TEXI2ROFF-KILL
+@include c-i960.texi
@end ifset
@ifset M680X0
-@ifset GENERIC
-@page
-@node M68K-Dependent
-@chapter M680x0 Dependent Features
+@include c-m68k.texi
@end ifset
-@ifclear GENERIC
-@node Machine Dependencies
-@chapter M680x0 Dependent Features
-@end ifclear
-
-@cindex M680x0 support
-@menu
-* M68K-Opts:: M680x0 Options
-* M68K-Syntax:: Syntax
-* M68K-Moto-Syntax:: Motorola Syntax
-* M68K-Float:: Floating Point
-* M68K-Directives:: 680x0 Machine Directives
-* M68K-opcodes:: Opcodes
-@end menu
-
-@node M68K-Opts
-@section M680x0 Options
-
-@cindex options, M680x0
-@cindex M680x0 options
-The Motorola 680x0 version of @code{@value{AS}} has two machine dependent options.
-One shortens undefined references from 32 to 16 bits, while the
-other is used to tell @code{@value{AS}} what kind of machine it is
-assembling for.
-
-@cindex @code{-l} option, M680x0
-You can use the @samp{-l} option to shorten the size of references to undefined
-symbols. If you do not use the @samp{-l} option, references to undefined
-symbols are wide enough for a full @code{long} (32 bits). (Since
-@code{@value{AS}} cannot know where these symbols end up, @code{@value{AS}} can
-only allocate space for the linker to fill in later. Since @code{@value{AS}}
-does not know how far away these symbols are, it allocates as much space as it
-can.) If you use this option, the references are only one word wide (16 bits).
-This may be useful if you want the object file to be as small as possible, and
-you know that the relevant symbols are always less than 17 bits away.
-
-@cindex @code{-m68000} and related options
-@cindex architecture options, M680x0
-@cindex M680x0 architecture options
-The 680x0 version of @code{@value{AS}} is most frequently used to assemble
-programs for the Motorola MC68020 microprocessor. Occasionally it is
-used to assemble programs for the mostly similar, but slightly different
-MC68000 or MC68010 microprocessors. You can give @code{@value{AS}} the options
-@samp{-m68000}, @samp{-mc68000}, @samp{-m68010}, @samp{-mc68010},
-@samp{-m68020}, and @samp{-mc68020} to tell it what processor is the
-target.
-
-@node M68K-Syntax
-@section Syntax
-
-@cindex @sc{mit}
-This syntax for the Motorola 680x0 was developed at @sc{mit}.
-
-@cindex M680x0 syntax
-@cindex syntax, M680x0
-@cindex M680x0 size modifiers
-@cindex size modifiers, M680x0
-The 680x0 version of @code{@value{AS}} uses syntax compatible with the Sun
-assembler. Intervening periods are ignored; for example, @samp{movl} is
-equivalent to @samp{move.l}.
-
-@ifset INTERNALS
-If @code{@value{AS}} is compiled with SUN_ASM_SYNTAX defined, it
-also allows Sun-style local labels of the form @samp{1$} through
-@samp{$9}.
-@end ifset
-
-In the following table @dfn{apc} stands for any of the address
-registers (@samp{a0} through @samp{a7}), nothing, (@samp{}), the
-Program Counter (@samp{pc}), or the zero-address relative to the
-program counter (@samp{zpc}).
-
-@cindex M680x0 addressing modes
-@cindex addressing modes, M680x0
-The following addressing modes are understood:
-@table @dfn
-@item Immediate
-@samp{#@var{digits}}
-
-@item Data Register
-@samp{%d0} through @samp{%d7}
-
-@item Address Register
-@samp{%a0} through @samp{%a7}@*
-@samp{%a7} is also known as @samp{%sp}, i.e. the Stack Pointer. @code{%a6}
-is also known as @samp{%fp}, the Frame Pointer.
-
-@item Address Register Indirect
-@samp{%a0@@} through @samp{%a7@@}
-
-@item Address Register Postincrement
-@samp{%a0@@+} through @samp{%a7@@+}
-
-@item Address Register Predecrement
-@samp{%a0@@-} through @samp{%a7@@-}
-
-@item Indirect Plus Offset
-@samp{%@var{apc}@@(@var{digits})}
-
-@item Index
-@samp{%@var{apc}@@(@var{digits},%@var{register}:@var{size}:@var{scale})}
-
-or @samp{%@var{apc}@@(%@var{register}:@var{size}:@var{scale})}
-
-@item Postindex
-@samp{%@var{apc}@@(@var{digits})@@(@var{digits},%@var{register}:@var{size}:@var{scale})}
-
-or @samp{%@var{apc}@@(@var{digits})@@(%@var{register}:@var{size}:@var{scale})}
-
-@item Preindex
-@samp{%@var{apc}@@(@var{digits},%@var{register}:@var{size}:@var{scale})@@(@var{digits})}
-
-or @samp{%@var{apc}@@(%@var{register}:@var{size}:@var{scale})@@(@var{digits})}
-
-@item Memory Indirect
-@samp{%@var{apc}@@(@var{digits})@@(@var{digits})}
-
-@item Absolute
-@samp{@var{symbol}}, or @samp{@var{digits}}
-@ignore
-@c pesch@cygnus.com: gnu, rich concur the following needs careful
-@c research before documenting.
- , or either of the above followed
-by @samp{:b}, @samp{:w}, or @samp{:l}.
-@end ignore
-@end table
-
-For some configurations, especially those where the compiler normally does not
-prepend an underscore to the names of user variables, the assembler requires a
-@samp{%} before any use of a register name. This is intended to let the
-assembler distinguish between C variables and registers named @samp{a0} through
-@samp{a7}, and so on. The @samp{%} is always accepted, but is not required for
-certain configurations, notably @samp{sun3}.
-
-@node M68K-Moto-Syntax
-@section Motorola Syntax
-
-@cindex Motorola syntax for the 680x0
-@cindex alternate syntax for the 680x0
-
-The standard Motorola syntax for this chip differs from the syntax already
-discussed (@pxref{M68K-Syntax,,Syntax}). @code{@value{AS}} can accept some
-forms of Motorola syntax for operands, even if @sc{mit} syntax is used for
-other operands in the same instruction. The two kinds of syntax are fully
-compatible; our support for Motorola syntax is simply incomplete at present.
-
-@cindex M680x0 syntax
-@cindex syntax, M680x0
-In particular, you may write or generate M68K assembler with the
-following conventions:
-
-(In the following table @dfn{%apc} stands for any of the address registers
-(@samp{%a0} through @samp{%a7}), nothing (@samp{}), the Program Counter
-(@samp{%pc}), or the zero-address relative to the program counter
-(@samp{%zpc}).)
-
-@cindex M680x0 addressing modes
-@cindex addressing modes, M680x0
-The following additional addressing modes are understood:
-@table @dfn
-@item Address Register Indirect
-@samp{%a0} through @samp{%a7}@*
-@samp{%a7} is also known as @samp{%sp}, i.e. the Stack Pointer. @code{%a6}
-is also known as @samp{%fp}, the Frame Pointer.
-
-@item Address Register Postincrement
-@samp{(%a0)+} through @samp{(%a7)+}
-
-@item Address Register Predecrement
-@samp{-(%a0)} through @samp{-(%a7)}
-
-@item Indirect Plus Offset
-@samp{@var{digits}(%@var{apc})}
-
-@item Index
-@samp{@var{digits}(%@var{apc},(%@var{register}.@var{size}*@var{scale}))}@*
-or @samp{(%@var{apc},%@var{register}.@var{size}*@var{scale})}@*
-In either case, @var{size} and @var{scale} are optional
-(@var{scale} defaults to @samp{1}, @var{size} defaults to @samp{l}).
- @var{scale} can be @samp{1}, @samp{2}, @samp{4}, or @samp{8}.
- @var{size} can be @samp{w} or @samp{l}. @var{scale} is only supported
-on the 68020 and greater.
-@end table
-
-Other, more complex addressing modes permitted in Motorola syntax are not
-handled.
-
-@node M68K-Float
-@section Floating Point
-
-@cindex floating point, M680x0
-@cindex M680x0 floating point
-@c FIXME is this "not too well tested" crud STILL true?
-The floating point code is not too well tested, and may have
-subtle bugs in it.
-
-Packed decimal (P) format floating literals are not supported.
-Feel free to add the code!
-
-The floating point formats generated by directives are these.
-
-@table @code
-@item .float
-@cindex @code{float} directive, M680x0
-@code{Single} precision floating point constants.
-
-@item .double
-@cindex @code{double} directive, M680x0
-@code{Double} precision floating point constants.
-@end table
-
-There is no directive to produce regions of memory holding
-extended precision numbers, however they can be used as
-immediate operands to floating-point instructions. Adding a
-directive to create extended precision numbers would not be
-hard, but it has not yet seemed necessary.
-
-@node M68K-Directives
-@section 680x0 Machine Directives
-
-@cindex M680x0 directives
-@cindex directives, M680x0
-In order to be compatible with the Sun assembler the 680x0 assembler
-understands the following directives.
-
-@table @code
-@item .data1
-@cindex @code{data1} directive, M680x0
-This directive is identical to a @code{.data 1} directive.
-
-@item .data2
-@cindex @code{data2} directive, M680x0
-This directive is identical to a @code{.data 2} directive.
-
-@item .even
-@cindex @code{even} directive, M680x0
-This directive is identical to a @code{.align 1} directive.
-@c Is this true? does it work???
-
-@item .skip
-@cindex @code{skip} directive, M680x0
-This directive is identical to a @code{.space} directive.
-@end table
-
-@need 2000
-@node M68K-opcodes
-@section Opcodes
-
-@cindex M680x0 opcodes
-@cindex opcodes, M680x0
-@cindex instruction set, M680x0
-@c pesch@cygnus.com: I don't see any point in the following
-@c paragraph. Bugs are bugs; how does saying this
-@c help anyone?
-@ignore
-Danger: Several bugs have been found in the opcode table (and
-fixed). More bugs may exist. Be careful when using obscure
-instructions.
-@end ignore
-
-@menu
-* M68K-Branch:: Branch Improvement
-* M68K-Chars:: Special Characters
-@end menu
-
-@node M68K-Branch
-@subsection Branch Improvement
-
-@cindex pseudo-opcodes, M680x0
-@cindex M680x0 pseudo-opcodes
-@cindex branch improvement, M680x0
-@cindex M680x0 branch improvement
-Certain pseudo opcodes are permitted for branch instructions.
-They expand to the shortest branch instruction that reach the
-target. Generally these mnemonics are made by substituting @samp{j} for
-@samp{b} at the start of a Motorola mnemonic.
-
-The following table summarizes the pseudo-operations. A @code{*} flags
-cases that are more fully described after the table:
-
-@smallexample
- Displacement
- +-------------------------------------------------
- | 68020 68000/10
-Pseudo-Op |BYTE WORD LONG LONG non-PC relative
- +-------------------------------------------------
- jbsr |bsrs bsr bsrl jsr jsr
- jra |bras bra bral jmp jmp
-* jXX |bXXs bXX bXXl bNXs;jmpl bNXs;jmp
-* dbXX |dbXX dbXX dbXX; bra; jmpl
-* fjXX |fbXXw fbXXw fbXXl fbNXw;jmp
-
-XX: condition
-NX: negative of condition XX
-
-@end smallexample
-@center @code{*}---see full description below
-
-@table @code
-@item jbsr
-@itemx jra
-These are the simplest jump pseudo-operations; they always map to one
-particular machine instruction, depending on the displacement to the
-branch target.
-
-@item j@var{XX}
-Here, @samp{j@var{XX}} stands for an entire family of pseudo-operations,
-where @var{XX} is a conditional branch or condition-code test. The full
-list of pseudo-ops in this family is:
-@smallexample
- jhi jls jcc jcs jne jeq jvc
- jvs jpl jmi jge jlt jgt jle
-@end smallexample
-
-For the cases of non-PC relative displacements and long displacements on
-the 68000 or 68010, @code{@value{AS}} issues a longer code fragment in terms of
-@var{NX}, the opposite condition to @var{XX}. For example, for the
-non-PC relative case:
-@smallexample
- j@var{XX} foo
-@end smallexample
-gives
-@smallexample
- b@var{NX}s oof
- jmp foo
- oof:
-@end smallexample
-
-@item db@var{XX}
-The full family of pseudo-operations covered here is
-@smallexample
- dbhi dbls dbcc dbcs dbne dbeq dbvc
- dbvs dbpl dbmi dbge dblt dbgt dble
- dbf dbra dbt
-@end smallexample
-
-Other than for word and byte displacements, when the source reads
-@samp{db@var{XX} foo}, @code{@value{AS}} emits
-@smallexample
- db@var{XX} oo1
- bra oo2
- oo1:jmpl foo
- oo2:
-@end smallexample
-
-@item fj@var{XX}
-This family includes
-@smallexample
- fjne fjeq fjge fjlt fjgt fjle fjf
- fjt fjgl fjgle fjnge fjngl fjngle fjngt
- fjnle fjnlt fjoge fjogl fjogt fjole fjolt
- fjor fjseq fjsf fjsne fjst fjueq fjuge
- fjugt fjule fjult fjun
-@end smallexample
-
-For branch targets that are not PC relative, @code{@value{AS}} emits
-@smallexample
- fb@var{NX} oof
- jmp foo
- oof:
-@end smallexample
-when it encounters @samp{fj@var{XX} foo}.
-
-@end table
-
-@node M68K-Chars
-@subsection Special Characters
-
-@cindex special characters, M680x0
-@cindex M680x0 immediate character
-@cindex immediate character, M680x0
-@cindex M680x0 line comment character
-@cindex line comment character, M680x0
-@cindex comments, M680x0
-The immediate character is @samp{#} for Sun compatibility. The
-line-comment character is @samp{|}. If a @samp{#} appears at the
-beginning of a line, it is treated as a comment unless it looks like
-@samp{# line file}, in which case it is treated normally.
-@end ifset
@ignore
@c FIXME! Stop ignoring when filled in.
@node 32x32
@@ -6440,1136 +4265,21 @@ only creates single or double precision values. I don't know if the
The 32x32 has no machine dependent directives.
@end ignore
+
@ifset SPARC
-@ifset GENERIC
-@page
-@node Sparc-Dependent
-@chapter SPARC Dependent Features
+@include c-sparc.texi
@end ifset
-@ifclear GENERIC
-@node Machine Dependencies
-@chapter SPARC Dependent Features
-@end ifclear
-
-@cindex SPARC support
-@menu
-* Sparc-Opts:: Options
-* Sparc-Float:: Floating Point
-* Sparc-Directives:: Sparc Machine Directives
-@end menu
-
-@node Sparc-Opts
-@section Options
-@cindex options for SPARC
-@cindex SPARC options
-@cindex architectures, SPARC
-@cindex SPARC architectures
-The SPARC chip family includes several successive levels (or other
-variants) of chip, using the same core instruction set, but including
-a few additional instructions at each level.
-
-By default, @code{@value{AS}} assumes the core instruction set (SPARC
-v6), but ``bumps'' the architecture level as needed: it switches to
-successively higher architectures as it encounters instructions that
-only exist in the higher levels.
-
-@table @code
-@item -Av6 | -Av7 | -Av8 | -Av9 | -Asparclite
-@kindex -Av6
-@kindex Av7
-@kindex -Av8
-@kindex -Av9
-@kindex -Asparclite
-Use one of the @samp{-A} options to select one of the SPARC
-architectures explicitly. If you select an architecture explicitly,
-@code{@value{AS}} reports a fatal error if it encounters an instruction
-or feature requiring a higher level.
-
-@item -bump
-Permit the assembler to ``bump'' the architecture level as required, but
-warn whenever it is necessary to switch to another level.
-@end table
-
-@ignore
-@c FIXME: (sparc) Fill in "syntax" section!
-@c subsection syntax
-I don't know anything about Sparc syntax. Someone who does
-will have to write this section.
-@end ignore
-
-@node Sparc-Float
-@section Floating Point
-
-@cindex floating point, SPARC (@sc{ieee})
-@cindex SPARC floating point (@sc{ieee})
-The Sparc uses @sc{ieee} floating-point numbers.
-
-@node Sparc-Directives
-@section Sparc Machine Directives
-
-@cindex SPARC machine directives
-@cindex machine directives, SPARC
-The Sparc version of @code{@value{AS}} supports the following additional
-machine directives:
-
-@table @code
-@item .align
-@cindex @code{align} directive, SPARC
-This must be followed by the desired alignment in bytes.
-
-@item .common
-@cindex @code{common} directive, SPARC
-This must be followed by a symbol name, a positive number, and
-@code{"bss"}. This behaves somewhat like @code{.comm}, but the
-syntax is different.
-
-@item .half
-@cindex @code{half} directive, SPARC
-This is functionally identical to @code{.short}.
-
-@item .proc
-@cindex @code{proc} directive, SPARC
-This directive is ignored. Any text following it on the same
-line is also ignored.
-
-@item .reserve
-@cindex @code{reserve} directive, SPARC
-This must be followed by a symbol name, a positive number, and
-@code{"bss"}. This behaves somewhat like @code{.lcomm}, but the
-syntax is different.
-
-@item .seg
-@cindex @code{seg} directive, SPARC
-This must be followed by @code{"text"}, @code{"data"}, or
-@code{"data1"}. It behaves like @code{.text}, @code{.data}, or
-@code{.data 1}.
-
-@item .skip
-@cindex @code{skip} directive, SPARC
-This is functionally identical to the @code{.space} directive.
-
-@item .word
-@cindex @code{word} directive, SPARC
-On the Sparc, the @code{.word} directive produces 32 bit values,
-instead of the 16 bit values it produces on many other machines.
-
-@item .xword
-@cindex @code{xword} directive, SPARC
-On the Sparc V9 processor, the @code{.xword} directive produces
-64 bit values.
-@end table
-
-@end ifset
@ifset I80386
-@ifset GENERIC
-@page
-@node i386-Dependent
-@chapter 80386 Dependent Features
+@include c-i386.texi
@end ifset
-@ifclear GENERIC
-@node Machine Dependencies
-@chapter 80386 Dependent Features
-@end ifclear
-
-@cindex i386 support
-@cindex i80306 support
-@menu
-* i386-Options:: Options
-* i386-Syntax:: AT&T Syntax versus Intel Syntax
-* i386-Opcodes:: Opcode Naming
-* i386-Regs:: Register Naming
-* i386-prefixes:: Opcode Prefixes
-* i386-Memory:: Memory References
-* i386-jumps:: Handling of Jump Instructions
-* i386-Float:: Floating Point
-* i386-16bit:: Writing 16-bit Code
-* i386-Notes:: Notes
-@end menu
-
-@node i386-Options
-@section Options
-
-@cindex options for i386 (none)
-@cindex i386 options (none)
-The 80386 has no machine dependent options.
-
-@node i386-Syntax
-@section AT&T Syntax versus Intel Syntax
-
-@cindex i386 syntax compatibility
-@cindex syntax compatibility, i386
-In order to maintain compatibility with the output of @code{@value{GCC}},
-@code{@value{AS}} supports AT&T System V/386 assembler syntax. This is quite
-different from Intel syntax. We mention these differences because
-almost all 80386 documents used only Intel syntax. Notable differences
-between the two syntaxes are:
-
-@itemize @bullet
-@item
-@cindex immediate operands, i386
-@cindex i386 immediate operands
-@cindex register operands, i386
-@cindex i386 register operands
-@cindex jump/call operands, i386
-@cindex i386 jump/call operands
-@cindex operand delimiters, i386
-AT&T immediate operands are preceded by @samp{$}; Intel immediate
-operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
-AT&T register operands are preceded by @samp{%}; Intel register operands
-are undelimited. AT&T absolute (as opposed to PC relative) jump/call
-operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
-
-@item
-@cindex i386 source, destination operands
-@cindex source, destination operands; i386
-AT&T and Intel syntax use the opposite order for source and destination
-operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
-@samp{source, dest} convention is maintained for compatibility with
-previous Unix assemblers.
-
-@item
-@cindex opcode suffixes, i386
-@cindex sizes operands, i386
-@cindex i386 size suffixes
-In AT&T syntax the size of memory operands is determined from the last
-character of the opcode name. Opcode suffixes of @samp{b}, @samp{w},
-and @samp{l} specify byte (8-bit), word (16-bit), and long (32-bit)
-memory references. Intel syntax accomplishes this by prefixes memory
-operands (@emph{not} the opcodes themselves) with @samp{byte ptr},
-@samp{word ptr}, and @samp{dword ptr}. Thus, Intel @samp{mov al, byte
-ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T syntax.
-
-@item
-@cindex return instructions, i386
-@cindex i386 jump, call, return
-Immediate form long jumps and calls are
-@samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
-Intel syntax is
-@samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
-instruction
-is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
-@samp{ret far @var{stack-adjust}}.
-
-@item
-@cindex sections, i386
-@cindex i386 sections
-The AT&T assembler does not provide support for multiple section
-programs. Unix style systems expect all programs to be single sections.
-@end itemize
-
-@node i386-Opcodes
-@section Opcode Naming
-
-@cindex i386 opcode naming
-@cindex opcode naming, i386
-Opcode names are suffixed with one character modifiers which specify the
-size of operands. The letters @samp{b}, @samp{w}, and @samp{l} specify
-byte, word, and long operands. If no suffix is specified by an
-instruction and it contains no memory operands then @code{@value{AS}} tries to
-fill in the missing suffix based on the destination register operand
-(the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
-to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
-@samp{movw $1, %bx}. Note that this is incompatible with the AT&T Unix
-assembler which assumes that a missing opcode suffix implies long
-operand size. (This incompatibility does not affect compiler output
-since compilers always explicitly specify the opcode suffix.)
-
-Almost all opcodes have the same names in AT&T and Intel format. There
-are a few exceptions. The sign extend and zero extend instructions need
-two sizes to specify them. They need a size to sign/zero extend
-@emph{from} and a size to zero extend @emph{to}. This is accomplished
-by using two opcode suffixes in AT&T syntax. Base names for sign extend
-and zero extend are @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T
-syntax (@samp{movsx} and @samp{movzx} in Intel syntax). The opcode
-suffixes are tacked on to this base name, the @emph{from} suffix before
-the @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
-``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
-thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
-and @samp{wl} (from word to long).
-
-@cindex conversion instructions, i386
-@cindex i386 conversion instructions
-The Intel-syntax conversion instructions
-
-@itemize @bullet
-@item
-@samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
-
-@item
-@samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
-
-@item
-@samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
-
-@item
-@samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
-@end itemize
-
-@noindent
-are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, and @samp{cltd} in
-AT&T naming. @code{@value{AS}} accepts either naming for these instructions.
-
-@cindex jump instructions, i386
-@cindex call instructions, i386
-Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
-AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
-convention.
-
-@node i386-Regs
-@section Register Naming
-
-@cindex i386 registers
-@cindex registers, i386
-Register operands are always prefixes with @samp{%}. The 80386 registers
-consist of
-
-@itemize @bullet
-@item
-the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
-@samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
-frame pointer), and @samp{%esp} (the stack pointer).
-
-@item
-the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
-@samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
-
-@item
-the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
-@samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
-are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
-@samp{%cx}, and @samp{%dx})
-
-@item
-the 6 section registers @samp{%cs} (code section), @samp{%ds}
-(data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
-and @samp{%gs}.
-
-@item
-the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
-@samp{%cr3}.
-
-@item
-the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
-@samp{%db3}, @samp{%db6}, and @samp{%db7}.
-
-@item
-the 2 test registers @samp{%tr6} and @samp{%tr7}.
-
-@item
-the 8 floating point register stack @samp{%st} or equivalently
-@samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
-@samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
-@end itemize
-
-@node i386-prefixes
-@section Opcode Prefixes
-
-@cindex i386 opcode prefixes
-@cindex opcode prefixes, i386
-@cindex prefixes, i386
-Opcode prefixes are used to modify the following opcode. They are used
-to repeat string instructions, to provide section overrides, to perform
-bus lock operations, and to give operand and address size (16-bit
-operands are specified in an instruction by prefixing what would
-normally be 32-bit operands with a ``operand size'' opcode prefix).
-Opcode prefixes are usually given as single-line instructions with no
-operands, and must directly precede the instruction they act upon. For
-example, the @samp{scas} (scan string) instruction is repeated with:
-@smallexample
- repne
- scas
-@end smallexample
-
-Here is a list of opcode prefixes:
-
-@itemize @bullet
-@item
-@cindex section override prefixes, i386
-Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
-@samp{fs}, @samp{gs}. These are automatically added by specifying
-using the @var{section}:@var{memory-operand} form for memory references.
-
-@item
-@cindex size prefixes, i386
-Operand/Address size prefixes @samp{data16} and @samp{addr16}
-change 32-bit operands/addresses into 16-bit operands/addresses. Note
-that 16-bit addressing modes (i.e. 8086 and 80286 addressing modes)
-are not supported (yet).
-
-@item
-@cindex bus lock prefixes, i386
-@cindex inhibiting interrupts, i386
-The bus lock prefix @samp{lock} inhibits interrupts during
-execution of the instruction it precedes. (This is only valid with
-certain instructions; see a 80386 manual for details).
-
-@item
-@cindex coprocessor wait, i386
-The wait for coprocessor prefix @samp{wait} waits for the
-coprocessor to complete the current instruction. This should never be
-needed for the 80386/80387 combination.
-@item
-@cindex repeat prefixes, i386
-The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
-to string instructions to make them repeat @samp{%ecx} times.
-@end itemize
-
-@node i386-Memory
-@section Memory References
-
-@cindex i386 memory references
-@cindex memory references, i386
-An Intel syntax indirect memory reference of the form
-
-@smallexample
-@var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
-@end smallexample
-
-@noindent
-is translated into the AT&T syntax
-
-@smallexample
-@var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
-@end smallexample
-
-@noindent
-where @var{base} and @var{index} are the optional 32-bit base and
-index registers, @var{disp} is the optional displacement, and
-@var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
-to calculate the address of the operand. If no @var{scale} is
-specified, @var{scale} is taken to be 1. @var{section} specifies the
-optional section register for the memory operand, and may override the
-default section register (see a 80386 manual for section register
-defaults). Note that section overrides in AT&T syntax @emph{must} have
-be preceded by a @samp{%}. If you specify a section override which
-coincides with the default section register, @code{@value{AS}} does @emph{not}
-output any section register override prefixes to assemble the given
-instruction. Thus, section overrides can be specified to emphasize which
-section register is used for a given memory operand.
-
-Here are some examples of Intel and AT&T style memory references:
-
-@table @asis
-@item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
-@var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
-missing, and the default section is used (@samp{%ss} for addressing with
-@samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
-
-@item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
-@var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
-@samp{foo}. All other fields are missing. The section register here
-defaults to @samp{%ds}.
-
-@item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
-This uses the value pointed to by @samp{foo} as a memory operand.
-Note that @var{base} and @var{index} are both missing, but there is only
-@emph{one} @samp{,}. This is a syntactic exception.
-
-@item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
-This selects the contents of the variable @samp{foo} with section
-register @var{section} being @samp{%gs}.
-@end table
-
-Absolute (as opposed to PC relative) call and jump operands must be
-prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
-always chooses PC relative addressing for jump/call labels.
-
-Any instruction that has a memory operand @emph{must} specify its size (byte,
-word, or long) with an opcode suffix (@samp{b}, @samp{w}, or @samp{l},
-respectively).
-
-@node i386-jumps
-@section Handling of Jump Instructions
-
-@cindex jump optimization, i386
-@cindex i386 jump optimization
-Jump instructions are always optimized to use the smallest possible
-displacements. This is accomplished by using byte (8-bit) displacement
-jumps whenever the target is sufficiently close. If a byte displacement
-is insufficient a long (32-bit) displacement is used. We do not support
-word (16-bit) displacement jumps (i.e. prefixing the jump instruction
-with the @samp{addr16} opcode prefix), since the 80386 insists upon masking
-@samp{%eip} to 16 bits after the word displacement is added.
-
-Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
-@samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
-displacements, so that if you use these instructions (@code{@value{GCC}} does
-not use them) you may get an error message (and incorrect code). The AT&T
-80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
-to
-
-@smallexample
- jcxz cx_zero
- jmp cx_nonzero
-cx_zero: jmp foo
-cx_nonzero:
-@end smallexample
-
-@node i386-Float
-@section Floating Point
-
-@cindex i386 floating point
-@cindex floating point, i386
-All 80387 floating point types except packed BCD are supported.
-(BCD support may be added without much difficulty). These data
-types are 16-, 32-, and 64- bit integers, and single (32-bit),
-double (64-bit), and extended (80-bit) precision floating point.
-Each supported type has an opcode suffix and a constructor
-associated with it. Opcode suffixes specify operand's data
-types. Constructors build these data types into memory.
-
-@itemize @bullet
-@item
-@cindex @code{float} directive, i386
-@cindex @code{single} directive, i386
-@cindex @code{double} directive, i386
-@cindex @code{tfloat} directive, i386
-Floating point constructors are @samp{.float} or @samp{.single},
-@samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
-These correspond to opcode suffixes @samp{s}, @samp{l}, and @samp{t}.
-@samp{t} stands for temporary real, and that the 80387 only supports
-this format via the @samp{fldt} (load temporary real to stack top) and
-@samp{fstpt} (store temporary real and pop stack) instructions.
-
-@item
-@cindex @code{word} directive, i386
-@cindex @code{long} directive, i386
-@cindex @code{int} directive, i386
-@cindex @code{quad} directive, i386
-Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
-@samp{.quad} for the 16-, 32-, and 64-bit integer formats. The corresponding
-opcode suffixes are @samp{s} (single), @samp{l} (long), and @samp{q}
-(quad). As with the temporary real format the 64-bit @samp{q} format is
-only present in the @samp{fildq} (load quad integer to stack top) and
-@samp{fistpq} (store quad integer and pop stack) instructions.
-@end itemize
-
-Register to register operations do not require opcode suffixes,
-so that @samp{fst %st, %st(1)} is equivalent to @samp{fstl %st, %st(1)}.
-
-@cindex i386 @code{fwait} instruction
-@cindex @code{fwait instruction}, i386
-Since the 80387 automatically synchronizes with the 80386 @samp{fwait}
-instructions are almost never needed (this is not the case for the
-80286/80287 and 8086/8087 combinations). Therefore, @code{@value{AS}} suppresses
-the @samp{fwait} instruction whenever it is implicitly selected by one
-of the @samp{fn@dots{}} instructions. For example, @samp{fsave} and
-@samp{fnsave} are treated identically. In general, all the @samp{fn@dots{}}
-instructions are made equivalent to @samp{f@dots{}} instructions. If
-@samp{fwait} is desired it must be explicitly coded.
-
-@node i386-16bit
-@section Writing 16-bit Code
-
-@cindex i386 16-bit code
-@cindex 16-bit code, i386
-@cindex real-mode code, i386
-@cindex @code{code16} directive, i386
-@cindex @code{code32} directive, i386
-While GAS normally writes only ``pure'' 32-bit i386 code, it has limited
-support for writing code to run in real mode or in 16-bit protected mode
-code segments. To do this, insert a @samp{.code16} directive before the
-assembly language instructions to be run in 16-bit mode. You can switch
-GAS back to writing normal 32-bit code with the @samp{.code32} directive.
-
-GAS understands exactly the same assembly language syntax in 16-bit mode as
-in 32-bit mode. The function of any given instruction is exactly the same
-regardless of mode, as long as the resulting object code is executed in the
-mode for which GAS wrote it. So, for example, the @samp{ret} mnemonic
-produces a 32-bit return instruction regardless of whether it is to be run
-in 16-bit or 32-bit mode. (If GAS is in 16-bit mode, it will add an
-operand size prefix to the instruction to force it to be a 32-bit return.)
-
-This means, for one thing, that you can use GNU CC to write code to be run
-in real mode or 16-bit protected mode. Just insert the statement
-@samp{asm(".code16");} at the beginning of your C source file, and while
-GNU CC will still be generating 32-bit code, GAS will automatically add all
-the necessary size prefixes to make that code run in 16-bit mode. Of
-course, since GNU CC only writes small-model code (it doesn't know how to
-attach segment selectors to pointers like native x86 compilers do), any
-16-bit code you write with GNU CC will essentially be limited to a 64K
-address space. Also, there will be a code size and performance penalty
-due to all the extra address and operand size prefixes GAS has to add to
-the instructions.
-
-Note that placing GAS in 16-bit mode does not mean that the resulting
-code will necessarily run on a 16-bit pre-80386 processor. To write code
-that runs on such a processor, you would have to refrain from using
-@emph{any} 32-bit constructs which require GAS to output address or
-operand size prefixes. At the moment this would be rather difficult,
-because GAS currently supports @emph{only} 32-bit addressing modes: when
-writing 16-bit code, it @emph{always} outputs address size prefixes for any
-instruction that uses a non-register addressing mode. So you can write
-code that runs on 16-bit processors, but only if that code never references
-memory.
-
-@node i386-Notes
-@section Notes
-
-@cindex i386 @code{mul}, @code{imul} instructions
-@cindex @code{mul} instruction, i386
-@cindex @code{imul} instruction, i386
-There is some trickery concerning the @samp{mul} and @samp{imul}
-instructions that deserves mention. The 16-, 32-, and 64-bit expanding
-multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
-for @samp{imul}) can be output only in the one operand form. Thus,
-@samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
-the expanding multiply would clobber the @samp{%edx} register, and this
-would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
-64-bit product in @samp{%edx:%eax}.
-
-We have added a two operand form of @samp{imul} when the first operand
-is an immediate mode expression and the second operand is a register.
-This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
-example, can be done with @samp{imul $69, %eax} rather than @samp{imul
-$69, %eax, %eax}.
-
-@end ifset
@ifset Z8000
-@ifset GENERIC
-@page
-@node Z8000-Dependent
-@chapter Z8000 Dependent Features
-@end ifset
-@ifclear GENERIC
-@node Machine Dependencies
-@chapter Z8000 Dependent Features
-@end ifclear
-
-@cindex Z8000 support
-The Z8000 @value{AS} supports both members of the Z8000 family: the
-unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with
-24 bit addresses.
-
-When the assembler is in unsegmented mode (specified with the
-@code{unsegm} directive), an address takes up one word (16 bit)
-sized register. When the assembler is in segmented mode (specified with
-the @code{segm} directive), a 24-bit address takes up a long (32 bit)
-register. @xref{Z8000 Directives,,Assembler Directives for the Z8000},
-for a list of other Z8000 specific assembler directives.
-
-@menu
-* Z8000 Options:: No special command-line options for Z8000
-* Z8000 Syntax:: Assembler syntax for the Z8000
-* Z8000 Directives:: Special directives for the Z8000
-* Z8000 Opcodes:: Opcodes
-@end menu
-
-@node Z8000 Options
-@section Options
-
-@cindex Z8000 options
-@cindex options, Z8000
-@code{@value{AS}} has no additional command-line options for the Zilog
-Z8000 family.
-
-@node Z8000 Syntax
-@section Syntax
-@menu
-* Z8000-Chars:: Special Characters
-* Z8000-Regs:: Register Names
-* Z8000-Addressing:: Addressing Modes
-@end menu
-
-@node Z8000-Chars
-@subsection Special Characters
-
-@cindex line comment character, Z8000
-@cindex Z8000 line comment character
-@samp{!} is the line comment character.
-
-@cindex line separator, Z8000
-@cindex statement separator, Z8000
-@cindex Z8000 line separator
-You can use @samp{;} instead of a newline to separate statements.
-
-@node Z8000-Regs
-@subsection Register Names
-
-@cindex Z8000 registers
-@cindex registers, Z8000
-The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer
-to different sized groups of registers by register number, with the
-prefix @samp{r} for 16 bit registers, @samp{rr} for 32 bit registers and
-@samp{rq} for 64 bit registers. You can also refer to the contents of
-the first eight (of the sixteen 16 bit registers) by bytes. They are
-named @samp{r@var{n}h} and @samp{r@var{n}l}.
-
-@smallexample
-@exdent @emph{byte registers}
-r0l r0h r1h r1l r2h r2l r3h r3l
-r4h r4l r5h r5l r6h r6l r7h r7l
-
-@exdent @emph{word registers}
-r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
-
-@exdent @emph{long word registers}
-rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14
-
-@exdent @emph{quad word registers}
-rq0 rq4 rq8 rq12
-@end smallexample
-
-@node Z8000-Addressing
-@subsection Addressing Modes
-
-@cindex addressing modes, Z8000
-@cindex Z800 addressing modes
-@value{AS} understands the following addressing modes for the Z8000:
-
-@table @code
-@item r@var{n}
-Register direct
-
-@item @@r@var{n}
-Indirect register
-
-@item @var{addr}
-Direct: the 16 bit or 24 bit address (depending on whether the assembler
-is in segmented or unsegmented mode) of the operand is in the instruction.
-
-@item address(r@var{n})
-Indexed: the 16 or 24 bit address is added to the 16 bit register to produce
-the final address in memory of the operand.
-
-@item r@var{n}(#@var{imm})
-Base Address: the 16 or 24 bit register is added to the 16 bit sign
-extended immediate displacement to produce the final address in memory
-of the operand.
-
-@item r@var{n}(r@var{m})
-Base Index: the 16 or 24 bit register r@var{n} is added to the sign
-extended 16 bit index register r@var{m} to produce the final address in
-memory of the operand.
-
-@item #@var{xx}
-Immediate data @var{xx}.
-@end table
-
-@node Z8000 Directives
-@section Assembler Directives for the Z8000
-
-@cindex Z8000 directives
-@cindex directives, Z8000
-The Z8000 port of @value{AS} includes these additional assembler directives,
-for compatibility with other Z8000 assemblers. As shown, these do not
-begin with @samp{.} (unlike the ordinary @value{AS} directives).
-
-@table @code
-@item segm
-@kindex segm
-Generates code for the segmented Z8001.
-
-@item unsegm
-@kindex unsegm
-Generates code for the unsegmented Z8002.
-
-@item name
-@kindex name
-Synonym for @code{.file}
-
-@item global
-@kindex global
-Synonum for @code{.global}
-
-@item wval
-@kindex wval
-Synonym for @code{.word}
-
-@item lval
-@kindex lval
-Synonym for @code{.long}
-
-@item bval
-@kindex bval
-Synonym for @code{.byte}
-
-@item sval
-@kindex sval
-Assemble a string. @code{sval} expects one string literal, delimited by
-single quotes. It assembles each byte of the string into consecutive
-addresses. You can use the escape sequence @samp{%@var{xx}} (where
-@var{xx} represents a two-digit hexadecimal number) to represent the
-character whose @sc{ascii} value is @var{xx}. Use this feature to
-describe single quote and other characters that may not appear in string
-literals as themselves. For example, the C statement @w{@samp{char *a =
-"he said \"it's 50% off\"";}} is represented in Z8000 assembly language
-(shown with the assembler output in hex at the left) as
-
-@iftex
-@begingroup
-@let@nonarrowing=@comment
-@end iftex
-@smallexample
-68652073 sval 'he said %22it%27s 50%25 off%22%00'
-61696420
-22697427
-73203530
-25206F66
-662200
-@end smallexample
-@iftex
-@endgroup
-@end iftex
-
-@item rsect
-@kindex rsect
-synonym for @code{.section}
-
-@item block
-@kindex block
-synonym for @code{.space}
-
-@item even
-@kindex even
-synonym for @code{.align 1}
-@end table
-
-@node Z8000 Opcodes
-@section Opcodes
-
-@cindex Z8000 opcode summary
-@cindex opcode summary, Z8000
-@cindex mnemonics, Z8000
-@cindex instruction summary, Z8000
-For detailed information on the Z8000 machine instruction set, see
-@cite{Z8000 Technical Manual}.
-
-@ifset SMALL
-@c this table, due to the multi-col faking and hardcoded order, looks silly
-@c except in smallbook. See comments below "@set SMALL" near top of this file.
-
-The following table summarizes the opcodes and their arguments:
-@iftex
-@begingroup
-@let@nonarrowing=@comment
-@end iftex
-@smallexample
-
- rs @r{16 bit source register}
- rd @r{16 bit destination register}
- rbs @r{8 bit source register}
- rbd @r{8 bit destination register}
- rrs @r{32 bit source register}
- rrd @r{32 bit destination register}
- rqs @r{64 bit source register}
- rqd @r{64 bit destination register}
- addr @r{16/24 bit address}
- imm @r{immediate data}
-
-adc rd,rs clrb addr cpsir @@rd,@@rs,rr,cc
-adcb rbd,rbs clrb addr(rd) cpsirb @@rd,@@rs,rr,cc
-add rd,@@rs clrb rbd dab rbd
-add rd,addr com @@rd dbjnz rbd,disp7
-add rd,addr(rs) com addr dec @@rd,imm4m1
-add rd,imm16 com addr(rd) dec addr(rd),imm4m1
-add rd,rs com rd dec addr,imm4m1
-addb rbd,@@rs comb @@rd dec rd,imm4m1
-addb rbd,addr comb addr decb @@rd,imm4m1
-addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1
-addb rbd,imm8 comb rbd decb addr,imm4m1
-addb rbd,rbs comflg flags decb rbd,imm4m1
-addl rrd,@@rs cp @@rd,imm16 di i2
-addl rrd,addr cp addr(rd),imm16 div rrd,@@rs
-addl rrd,addr(rs) cp addr,imm16 div rrd,addr
-addl rrd,imm32 cp rd,@@rs div rrd,addr(rs)
-addl rrd,rrs cp rd,addr div rrd,imm16
-and rd,@@rs cp rd,addr(rs) div rrd,rs
-and rd,addr cp rd,imm16 divl rqd,@@rs
-and rd,addr(rs) cp rd,rs divl rqd,addr
-and rd,imm16 cpb @@rd,imm8 divl rqd,addr(rs)
-and rd,rs cpb addr(rd),imm8 divl rqd,imm32
-andb rbd,@@rs cpb addr,imm8 divl rqd,rrs
-andb rbd,addr cpb rbd,@@rs djnz rd,disp7
-andb rbd,addr(rs) cpb rbd,addr ei i2
-andb rbd,imm8 cpb rbd,addr(rs) ex rd,@@rs
-andb rbd,rbs cpb rbd,imm8 ex rd,addr
-bit @@rd,imm4 cpb rbd,rbs ex rd,addr(rs)
-bit addr(rd),imm4 cpd rd,@@rs,rr,cc ex rd,rs
-bit addr,imm4 cpdb rbd,@@rs,rr,cc exb rbd,@@rs
-bit rd,imm4 cpdr rd,@@rs,rr,cc exb rbd,addr
-bit rd,rs cpdrb rbd,@@rs,rr,cc exb rbd,addr(rs)
-bitb @@rd,imm4 cpi rd,@@rs,rr,cc exb rbd,rbs
-bitb addr(rd),imm4 cpib rbd,@@rs,rr,cc ext0e imm8
-bitb addr,imm4 cpir rd,@@rs,rr,cc ext0f imm8
-bitb rbd,imm4 cpirb rbd,@@rs,rr,cc ext8e imm8
-bitb rbd,rs cpl rrd,@@rs ext8f imm8
-bpt cpl rrd,addr exts rrd
-call @@rd cpl rrd,addr(rs) extsb rd
-call addr cpl rrd,imm32 extsl rqd
-call addr(rd) cpl rrd,rrs halt
-calr disp12 cpsd @@rd,@@rs,rr,cc in rd,@@rs
-clr @@rd cpsdb @@rd,@@rs,rr,cc in rd,imm16
-clr addr cpsdr @@rd,@@rs,rr,cc inb rbd,@@rs
-clr addr(rd) cpsdrb @@rd,@@rs,rr,cc inb rbd,imm16
-clr rd cpsi @@rd,@@rs,rr,cc inc @@rd,imm4m1
-clrb @@rd cpsib @@rd,@@rs,rr,cc inc addr(rd),imm4m1
-inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs)
-inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16
-incb @@rd,imm4m1 ldb rd(rx),rbs mult rrd,rs
-incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@@rs
-incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr
-incb rbd,imm4m1 ldd @@rs,@@rd,rr multl rqd,addr(rs)
-ind @@rd,@@rs,ra lddb @@rs,@@rd,rr multl rqd,imm32
-indb @@rd,@@rs,rba lddr @@rs,@@rd,rr multl rqd,rrs
-inib @@rd,@@rs,ra lddrb @@rs,@@rd,rr neg @@rd
-inibr @@rd,@@rs,ra ldi @@rd,@@rs,rr neg addr
-iret ldib @@rd,@@rs,rr neg addr(rd)
-jp cc,@@rd ldir @@rd,@@rs,rr neg rd
-jp cc,addr ldirb @@rd,@@rs,rr negb @@rd
-jp cc,addr(rd) ldk rd,imm4 negb addr
-jr cc,disp8 ldl @@rd,rrs negb addr(rd)
-ld @@rd,imm16 ldl addr(rd),rrs negb rbd
-ld @@rd,rs ldl addr,rrs nop
-ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@@rs
-ld addr(rd),rs ldl rd(rx),rrs or rd,addr
-ld addr,imm16 ldl rrd,@@rs or rd,addr(rs)
-ld addr,rs ldl rrd,addr or rd,imm16
-ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs
-ld rd(rx),rs ldl rrd,imm32 orb rbd,@@rs
-ld rd,@@rs ldl rrd,rrs orb rbd,addr
-ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs)
-ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8
-ld rd,imm16 ldm @@rd,rs,n orb rbd,rbs
-ld rd,rs ldm addr(rd),rs,n out @@rd,rs
-ld rd,rs(imm16) ldm addr,rs,n out imm16,rs
-ld rd,rs(rx) ldm rd,@@rs,n outb @@rd,rbs
-lda rd,addr ldm rd,addr(rs),n outb imm16,rbs
-lda rd,addr(rs) ldm rd,addr,n outd @@rd,@@rs,ra
-lda rd,rs(imm16) ldps @@rs outdb @@rd,@@rs,rba
-lda rd,rs(rx) ldps addr outib @@rd,@@rs,ra
-ldar rd,disp16 ldps addr(rs) outibr @@rd,@@rs,ra
-ldb @@rd,imm8 ldr disp16,rs pop @@rd,@@rs
-ldb @@rd,rbs ldr rd,disp16 pop addr(rd),@@rs
-ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@@rs
-ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@@rs
-ldb addr,imm8 ldrl disp16,rrs popl @@rd,@@rs
-ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@@rs
-ldb rbd,@@rs mbit popl addr,@@rs
-ldb rbd,addr mreq rd popl rrd,@@rs
-ldb rbd,addr(rs) mres push @@rd,@@rs
-ldb rbd,imm8 mset push @@rd,addr
-ldb rbd,rbs mult rrd,@@rs push @@rd,addr(rs)
-ldb rbd,rs(imm16) mult rrd,addr push @@rd,imm16
-push @@rd,rs set addr,imm4 subl rrd,imm32
-pushl @@rd,@@rs set rd,imm4 subl rrd,rrs
-pushl @@rd,addr set rd,rs tcc cc,rd
-pushl @@rd,addr(rs) setb @@rd,imm4 tccb cc,rbd
-pushl @@rd,rrs setb addr(rd),imm4 test @@rd
-res @@rd,imm4 setb addr,imm4 test addr
-res addr(rd),imm4 setb rbd,imm4 test addr(rd)
-res addr,imm4 setb rbd,rs test rd
-res rd,imm4 setflg imm4 testb @@rd
-res rd,rs sinb rbd,imm16 testb addr
-resb @@rd,imm4 sinb rd,imm16 testb addr(rd)
-resb addr(rd),imm4 sind @@rd,@@rs,ra testb rbd
-resb addr,imm4 sindb @@rd,@@rs,rba testl @@rd
-resb rbd,imm4 sinib @@rd,@@rs,ra testl addr
-resb rbd,rs sinibr @@rd,@@rs,ra testl addr(rd)
-resflg imm4 sla rd,imm8 testl rrd
-ret cc slab rbd,imm8 trdb @@rd,@@rs,rba
-rl rd,imm1or2 slal rrd,imm8 trdrb @@rd,@@rs,rba
-rlb rbd,imm1or2 sll rd,imm8 trib @@rd,@@rs,rbr
-rlc rd,imm1or2 sllb rbd,imm8 trirb @@rd,@@rs,rbr
-rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @@ra,@@rb,rbr
-rldb rbb,rba sout imm16,rs trtib @@ra,@@rb,rr
-rr rd,imm1or2 soutb imm16,rbs trtirb @@ra,@@rb,rbr
-rrb rbd,imm1or2 soutd @@rd,@@rs,ra trtrb @@ra,@@rb,rbr
-rrc rd,imm1or2 soutdb @@rd,@@rs,rba tset @@rd
-rrcb rbd,imm1or2 soutib @@rd,@@rs,ra tset addr
-rrdb rbb,rba soutibr @@rd,@@rs,ra tset addr(rd)
-rsvd36 sra rd,imm8 tset rd
-rsvd38 srab rbd,imm8 tsetb @@rd
-rsvd78 sral rrd,imm8 tsetb addr
-rsvd7e srl rd,imm8 tsetb addr(rd)
-rsvd9d srlb rbd,imm8 tsetb rbd
-rsvd9f srll rrd,imm8 xor rd,@@rs
-rsvdb9 sub rd,@@rs xor rd,addr
-rsvdbf sub rd,addr xor rd,addr(rs)
-sbc rd,rs sub rd,addr(rs) xor rd,imm16
-sbcb rbd,rbs sub rd,imm16 xor rd,rs
-sc imm8 sub rd,rs xorb rbd,@@rs
-sda rd,rs subb rbd,@@rs xorb rbd,addr
-sdab rbd,rs subb rbd,addr xorb rbd,addr(rs)
-sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8
-sdl rd,rs subb rbd,imm8 xorb rbd,rbs
-sdlb rbd,rs subb rbd,rbs xorb rbd,rbs
-sdll rrd,rs subl rrd,@@rs
-set @@rd,imm4 subl rrd,addr
-set addr(rd),imm4 subl rrd,addr(rs)
-@end smallexample
-@iftex
-@endgroup
-@end iftex
-@end ifset
-
+@include c-z8k.texi
@end ifset
@ifset MIPS
-@ifset GENERIC
-@page
-@node MIPS-Dependent
-@chapter MIPS Dependent Features
-@end ifset
-@ifclear GENERIC
-@node Machine Dependencies
-@chapter MIPS Dependent Features
-@end ifclear
-
-@cindex MIPS R2000
-@cindex MIPS R3000
-@cindex MIPS R4000
-@cindex MIPS R6000
-@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports the @sc{mips}
-@sc{r2000}, @sc{r3000}, @sc{r4000} and @sc{r6000} processors. For information
-about the @sc{mips} instruction set, see @cite{MIPS RISC Architecture}, by Kane
-and Heindrich (Prentice-Hall). For an overview of @sc{mips} assembly
-conventions, see ``Appendix D: Assembly Language Programming'' in the same
-work.
-
-@menu
-* MIPS Opts:: Assembler options
-* MIPS Object:: ECOFF object code
-* MIPS Stabs:: Directives for debugging information
-* MIPS ISA:: Directives to override the ISA level
-@end menu
-
-@node MIPS Opts
-@section Assembler options
-
-The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
-special options:
-
-@table @code
-@cindex @code{-G} option (MIPS)
-@item -G @var{num}
-This option sets the largest size of an object that can be referenced
-implicitly with the @code{gp} register. It is only accepted for targets
-that use @sc{ecoff} format. The default value is 8.
-
-@cindex @code{-EB} option (MIPS)
-@cindex @code{-EL} option (MIPS)
-@cindex MIPS big-endian output
-@cindex MIPS little-endian output
-@cindex big-endian output, MIPS
-@cindex little-endian output, MIPS
-@item -EB
-@itemx -EL
-Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
-little-endian output at run time (unlike the other @sc{gnu} development
-tools, which must be configured for one or the other). Use @samp{-EB}
-to select big-endian output, and @samp{-EL} for little-endian.
-
-@cindex MIPS architecture options
-@item -mips1
-@itemx -mips2
-@itemx -mips3
-Generate code for a particular MIPS Instruction Set Architecture level.
-@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
-@samp{-mips2} to the @sc{r6000} processor, and @samp{-mips3} to the @sc{r4000}
-processor. You can also switch instruction sets during the assembly; see
-@ref{MIPS ISA,, Directives to override the ISA level}.
-
-@item -m4650
-@item -no-m4650
-Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept
-the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
-instructions around accesses to the @samp{HI} and @samp{LO} registers.
-@samp{-no-m4650} turns off this option.
-
-@item -mcpu=@var{CPU}
-Generate code for a particular MIPS cpu. This has little effect on the
-assembler, but it is passed by @code{@value{GCC}}.
-
-@cindex @code{-nocpp} ignored (MIPS)
-@item -nocpp
-This option is ignored. It is accepted for command-line compatibility with
-other assemblers, which use it to turn off C style preprocessing. With
-@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
-@sc{gnu} assembler itself never runs the C preprocessor.
-
-@item --trap
-@itemx --no-break
-@c FIXME! (1) reflect these options (next item too) in option summaries;
-@c (2) stop teasing, say _which_ instructions expanded _how_.
-@code{@value{AS}} automatically macro expands certain division and
-multiplication instructions to check for overflow and division by zero. This
-option causes @code{@value{AS}} to generate code to take a trap exception
-rather than a break exception when an error is detected. The trap instructions
-are only supported at Instruction Set Architecture level 2 and higher.
-
-@item --break
-@itemx --no-trap
-Generate code to take a break exception rather than a trap exception when an
-error is detected. This is the default.
-@end table
-
-@node MIPS Object
-@section MIPS ECOFF object code
-
-@cindex ECOFF sections
-@cindex MIPS ECOFF sections
-Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
-besides the usual @code{.text}, @code{.data} and @code{.bss}. The
-additional sections are @code{.rdata}, used for read-only data,
-@code{.sdata}, used for small data, and @code{.sbss}, used for small
-common objects.
-
-@cindex small objects, MIPS ECOFF
-@cindex @code{gp} register, MIPS
-When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
-register to form the address of a ``small object''. Any object in the
-@code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
-For external objects, or for objects in the @code{.bss} section, you can use
-the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
-@code{$gp}; the default value is 8, meaning that a reference to any object
-eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to
-@code{@value{AS}} prevents it from using the @code{$gp} register on the basis
-of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
-or @code{sbss} in any case). The size of an object in the @code{.bss} section
-is set by the @code{.comm} or @code{.lcomm} directive that defines it. The
-size of an external object may be set with the @code{.extern} directive. For
-example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
-in length, whie leaving @code{sym} otherwise undefined.
-
-Using small @sc{ecoff} objects requires linker support, and assumes that the
-@code{$gp} register is correctly initialized (normally done automatically by
-the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the
-@code{$gp} register.
-
-@node MIPS Stabs
-@section Directives for debugging information
-
-@cindex MIPS debugging directives
-@sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
-generating debugging information which are not support by traditional @sc{mips}
-assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
-@code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
-@code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information
-generated by the three @code{.stab} directives can only be read by @sc{gdb},
-not by traditional @sc{mips} debuggers (this enhancement is required to fully
-support C++ debugging). These directives are primarily used by compilers, not
-assembly language programmers!
-
-@node MIPS ISA
-@section Directives to override the ISA level
-
-@cindex MIPS ISA override
-@kindex @code{.set mips@var{n}}
-@sc{gnu} @code{@value{AS}} supports an additional directive to change the
-@sc{mips} Instruction Set Architecture level on the fly: @code{.set
-mips@var{n}}. @var{n} should be a number from 0 to 3. A value from 1 to 3
-makes the assembler accept instructions for the corresponding @sc{isa} level,
-from that point on in the assembly. @code{.set mips@var{n}} affects not only
-which instructions are permitted, but also how certain macros are expanded.
-@code{.set mips0} restores the @sc{isa} level to its original level: either the
-level you selected with command line options, or the default for your
-configuration. You can use this feature to permit specific @sc{r4000}
-instructions while assembling in 32 bit mode. Use this directive with care!
-
-Traditional @sc{mips} assemblers do not support this directive.
+@include c-mips.texi
@end ifset
@ifset GENERIC
@@ -7585,8 +4295,8 @@ it is not meant as a slight. We just don't know about it. Send mail to the
maintainer, and we'll correct the situation. Currently (January 1994), the
maintainer is Ken Raeburn (email address @code{raeburn@@cygnus.com}).
-Dean Elsner wrote the original @sc{gnu} assembler for the VAX.@footnote{Any more
-details?}
+Dean Elsner wrote the original @sc{gnu} assembler for the VAX.@footnote{Any
+more details?}
Jay Fenlason maintained GAS for a while, adding support for GDB-specific debug
information and the 68k series machines, most of the preprocessing pass, and
generated by cgit v1.1 at 2024-12-18 10:29:56 +0000