bfd ChangeLog

	* elf32-xtensa.c (elf32xtensa_size_opt): New global variable.
	(xtensa_default_isa): Global variable moved here from xtensa-isa.c.
	(elf32xtensa_no_literal_movement): New global variable.
	(elf_howto_table): Add entries for new relocations.
	(elf_xtensa_reloc_type_lookup): Handle new relocations.
	(property_table_compare): When addresses are equal, compare sizes and
	various property flags.
	(property_table_matches): New.
	(xtensa_read_table_entries): Extend to read new property tables.  Add
	output_addr parameter to indicate that output addresses should be used.
	Use bfd_get_section_limit.
	(elf_xtensa_find_property_entry): New.
	(elf_xtensa_in_literal_pool): Use elf_xtensa_find_property_entry.
	(elf_xtensa_check_relocs): Handle new relocations.
	(elf_xtensa_do_reloc): Use bfd_get_section_limit.  Handle new
	relocations.  Use new xtensa-isa.h functions.
	(build_encoding_error_message): Remove encode_result parameter.  Add
	new target_address parameter used to detect alignment errors.
	(elf_xtensa_relocate_section): Use bfd_get_section_limit.  Clean up
	error handling.  Use new is_operand_relocation function.
	(elf_xtensa_combine_prop_entries, elf_xtensa_merge_private_bfd_data):
	Use underbar macro for error messages.  Formatting.
	(get_const16_opcode): New.
	(get_l32r_opcode): Add a separate flag for initialization.
	(get_relocation_opnd): Operand number is no longer explicit in the
	relocation.  Change to decode the opcode and analyze its operands.
	(get_relocation_slot): New.
	(get_relocation_opcode): Add bfd parameter.  Use bfd_get_section_limit.
	Use new xtensa-isa.h functions to handle multislot instructions.
	(is_l32r_relocation): Add bfd parameter.  Use is_operand_relocation.
	(get_asm_simplify_size, is_alt_relocation, is_operand_relocation,
	insn_decode_len, insn_decode_opcode, check_branch_target_aligned,
	check_loop_aligned, check_branch_target_aligned_address, narrowable,
	widenable, narrow_instruction, widen_instruction, op_single_fmt_table,
	get_single_format, init_op_single_format_table): New.
	(elf_xtensa_do_asm_simplify): Add error_message parameter and use it
	instead of calling _bfd_error_handler.  Use new xtensa-isa.h functions.
	(contract_asm_expansion): Add error_message parameter and pass it to
	elf_xtensa_do_asm_simplify.  Replace use of R_XTENSA_OP0 relocation
	with R_XTENSA_SLOT0_OP.
	(get_expanded_call_opcode): Extend to handle either L32R or CONST16
	instructions.  Use new xtensa-isa.h functions.
	(r_reloc struct): Add new virtual_offset field.
	(r_reloc_init): Add contents and content_length parameters.  Set
	virtual_offset field to zero.  Add contents to target_offset field for
	partial_inplace relocations.
	(r_reloc_is_defined): Check for null.
	(print_r_reloc): New debug function.
	(source_reloc struct): Replace xtensa_operand field with pair of the
	opcode and the operand position.  Add is_abs_literal field.
	(init_source_reloc): Specify operand by opcode/position pair.  Set
	is_abs_literal field.
	(source_reloc_compare): When target_offsets are equal, compare other
	fields to make sorting predictable.
	(literal_value struct): Add is_abs_literal field.
	(value_map_hash_table struct): Add has_last_loc and last_loc fields.
	(init_literal_value): New.
	(is_same_value): Replace with ...
	(literal_value_equal): ... this function.  Add comparisons of
	virtual_offset and is_abs_literal fields.
	(value_map_hash_table_init): Use bfd_zmalloc.  Check for allocation
	failure.  Initialize has_last_loc field.
	(value_map_hash_table_delete): New.
	(hash_literal_value): Rename to ...
	(literal_value_hash): ... this.  Include is_abs_literal flag and
	virtual_offset field in the hash value.
	(get_cached_value): Rename to ...
	(value_map_get_cached_value): ... this.  Update calls to
	literal_value_hash and literal_value_equal.
	(add_value_map): Check for allocation failure.  Update calls to
	value_map_get_cached_value and literal_value_hash.
	(text_action, text_action_list, text_action_t): New types.
	(find_fill_action, compute_removed_action_diff, adjust_fill_action,
	text_action_add, text_action_add_literal, offset_with_removed_text,
	offset_with_removed_text_before_fill, find_insn_action,
	print_action_list, print_removed_literals): New.
	(offset_with_removed_literals): Delete.
	(xtensa_relax_info struct): Add is_relaxable_asm_section, action_list,
	fix_array, fix_array_count, allocated_relocs, relocs_count, and
	allocated_relocs_count fields.
	(init_xtensa_relax_info): Initialize new fields.
	(reloc_bfd_fix struct): Add new translated field.
	(reloc_bfd_fix_init): Add translated parameter and use it to set the
	translated field.
	(fix_compare, cache_fix_array): New.
	(get_bfd_fix): Remove fix_list parameter and get all relax_info for the
	section via get_xtensa_relax_info.  Use cache_fix_array to set up
	sorted fix_array and use bsearch instead of linear search.
	(section_cache_t): New struct.
	(init_section_cache, section_cache_section, clear_section_cache): New.
	(ebb_t, ebb_target_enum, proposed_action, ebb_constraint): New types.
	(init_ebb_constraint, free_ebb_constraint, init_ebb, extend_ebb_bounds,
	extend_ebb_bounds_forward, extend_ebb_bounds_backward,
	insn_block_decodable_len, ebb_propose_action, ebb_add_proposed_action):
	New.
	(retrieve_contents): Use bfd_get_section_limit.
	(elf_xtensa_relax_section): Add relocations_analyzed flag.  Update call
	to compute_removed_literals.  Free value_map_hash_table when no longer
	needed.
	(analyze_relocations): Check is_relaxable_asm_section flag.  Call
	compute_text_actions for all sections.
	(find_relaxable_sections): Mark sections as relaxable if they contain
	ASM_EXPAND relocations that can be optimized.  Adjust r_reloc_init
	call.  Increment relax_info src_count field only for appropriate
	relocation types.  Remove is_literal_section check.
	(collect_source_relocs): Use bfd_get_section_limit.  Adjust calls to
	r_reloc_init and find_associated_l32r_irel.  Check
	is_relaxable_asm_section flag.  Handle L32R instructions with absolute
	literals.  Pass is_abs_literal flag to init_source_reloc.
	(is_resolvable_asm_expansion): Use bfd_get_section_limit.  Check for
	CONST16 instructions.  Adjust calls to r_reloc_init and
	pcrel_reloc_fits.  Handle weak symbols conservatively.
	(find_associated_l32r_irel): Add bfd parameter and pass it to
	is_l32r_relocation.
	(compute_text_actions, compute_ebb_proposed_actions,
	compute_ebb_actions, check_section_ebb_pcrels_fit,
	check_section_ebb_reduces, text_action_add_proposed,
	compute_fill_extra_space): New.
	(remove_literals): Replace with ...
	(compute_removed_literals): ... this function.  Call
	init_section_cache.  Use bfd_get_section_limit.  Sort internal_relocs.
	Call xtensa_read_table_entries to get the property table.  Skip
	relocations other than R_XTENSA_32 and R_XTENSA_PLT.  Use new
	is_removable_literal, remove_dead_literal, and
	identify_literal_placement functions.
	(get_irel_at_offset): Rewrite to use bsearch on sorted relocations
	instead of linear search.
	(is_removable_literal, remove_dead_literal,
	identify_literal_placement): New.
	(relocations_reach): Update check for literal not referenced by any
	PC-relative relocations.  Adjust call to pcrel_reloc_fits.
	(coalesce_shared_literal, move_shared_literal): New.
	(relax_section): Use bfd_get_section_limit.  Call
	translate_section_fixes.  Update calls to r_reloc_init and
	offset_with_removed_text.  Check new is_relaxable_asm_section flag.
	Add call to pin_internal_relocs.  Add special handling for
	R_XTENSA_ASM_SIMPLIFY and R_XTENSA_DIFF* relocs.  Use virtual_offset
	info to calculate new addend_displacement variable.  Replace code for
	deleting literals with more general code to perform the actions
	determined by the action_list for the section.
	(translate_section_fixes, translate_reloc_bfd_fix): New.
	(translate_reloc): Check new is_relaxable_asm_section flag.  Call
	find_removed_literal only if is_operand_relocation.  Update call to
	offset_with_removed_text.  Use new target_offset and removed_bytes
	variables.
	(move_literal): New.
	(relax_property_section):  Use bfd_get_section_limit.  Set new
	is_full_prop_section flag and handle new property tables.  Update calls
	to r_reloc_init and offset_with_removed_text.  Check
	is_relaxable_asm_section flag.  Handle expansion of zero-sized
	unreachable entries, with use of offset_with_removed_text_before_fill.
	For relocatable links, combine entries only for literal tables.
	(relax_section_symbols): Check is_relaxable_asm_section flag.  Update
	calls to offset_with_removed_text.  Translate st_size field for
	function symbols.
	(do_fix_for_relocatable_link): Change to return bfd_boolean to indicate
	failure.  Add contents parameter.  Update call to get_bfd_fix.  Update
	call to r_reloc_init.  Call _bfd_error_handler and return FALSE for
	R_XTENSA_ASM_EXPAND relocs.
	(do_fix_for_final_link): Add input_bfd and contents parameters.  Update
	call to get_bfd_fix.  Include offset from contents for partial_inplace
	relocations.
	(is_reloc_sym_weak): New.
	(pcrel_reloc_fits): Use new xtensa-isa.h functions.
	(prop_sec_len): New.
	(xtensa_is_property_section): Handle new property sections.
	(is_literal_section): Delete.
	(internal_reloc_compare): When r_offset matches, compare r_info and
	r_addend to make sorting predictable.
	(internal_reloc_matches): New.
	(xtensa_get_property_section_name): Handle new property sections.
	(xtensa_get_property_predef_flags): New.
	(xtensa_callback_required_dependence): Use bfd_get_section_limit.
	Update calls to xtensa_isa_init, is_l32r_relocation, and r_reloc_init.
	* xtensa-isa.c (xtensa_default_isa): Moved to elf32-xtensa.c.
	(xtisa_errno, xtisa_error_msg): New variables.
	(xtensa_isa_errno, xtensa_isa_error_msg): New.
	(xtensa_insnbuf_alloc): Add error handling.
	(xtensa_insnbuf_to_chars): Add num_chars parameter.  Update to
	use xtensa_format_decode.  Add error handling.
	(xtensa_insnbuf_from_chars): Add num_chars parameter.  Decode the
	instruction length to find the number of bytes to copy.
	(xtensa_isa_init): Add error handling.  Replace calls to
	xtensa_load_isa and xtensa_extend_isa with code to initialize lookup
	tables in the xtensa_modules structure.
	(xtensa_check_isa_config, xtensa_add_isa, xtensa_load_isa,
	xtensa_extend_isa): Delete.
	(xtensa_isa_free): Change to only free lookup tables.
	(opname_lookup_compare): Replace with ...
	(xtensa_isa_name_compare): ... this function.  Use strcasecmp.
	(xtensa_insn_maxlength): Rename to ...
	(xtensa_isa_maxlength): ... this.
	(xtensa_insn_length): Delete.
	(xtensa_insn_length_from_first_byte): Replace with ...
	(xtensa_isa_length_from_chars): ... this function.
	(xtensa_num_opcodes): Rename to ...
	(xtensa_isa_num_opcodes): ... this.
	(xtensa_isa_num_pipe_stages, xtensa_isa_num_formats,
	xtensa_isa_num_regfiles, xtensa_isa_num_stages,
	xtensa_isa_num_sysregs, xtensa_isa_num_interfaces,
	xtensa_isa_num_funcUnits, xtensa_format_name, xtensa_format_lookup,
	xtensa_format_decode, xtensa_format_encode, xtensa_format_length,
	xtensa_format_num_slots, xtensa_format_slot_nop_opcode,
	xtensa_format_get_slot, xtensa_format_set_slot): New functions.
	(xtensa_opcode_lookup): Add error handling.
	(xtensa_decode_insn): Replace with ...
	(xtensa_opcode_decode): ... this function, with new format and
	slot parameters.  Add error handling.
	(xtensa_encode_insn): Replace with ...
	(xtensa_opcode_encode): ... this function, which does the encoding via
	one of the entries in the "encode_fns" array.  Add error handling.
	(xtensa_opcode_name): Add error handling.
	(xtensa_opcode_is_branch, xtensa_opcode_is_jump, xtensa_opcode_is_loop,
	xtensa_opcode_is_call): New.
	(xtensa_num_operands): Replace with ...
	(xtensa_opcode_num_operands): ... this function.  Add error handling.
	(xtensa_opcode_num_stateOperands,
	xtensa_opcode_num_interfaceOperands, xtensa_opcode_num_funcUnit_uses,
	xtensa_opcode_funcUnit_use, xtensa_operand_name,
	xtensa_operand_is_visible): New.
	(xtensa_get_operand, xtensa_operand_kind): Delete.
	(xtensa_operand_inout): Add error handling and special-case for
	"sout" operands.
	(xtensa_operand_get_field, xtensa_operand_set_field): Rewritten to
	operate on one slot of an instruction.  Added error handling.
	(xtensa_operand_encode): Handle default operands with no encoding
	functions.  Check for success by comparing against decoded value.
	Add error handling.
	(xtensa_operand_decode): Handle default operands.  Return decoded value
	through argument pointer.  Add error handling.
	(xtensa_operand_is_register, xtensa_operand_regfile,
	xtensa_operand_num_regs, xtensa_operand_is_known_reg): New.
	(xtensa_operand_isPCRelative): Rename to ...
	(xtensa_operand_is_PCrelative): ... this.  Add error handling.
	(xtensa_operand_do_reloc, xtensa_operand_undo_reloc): Return value
	through argument pointer.  Add error handling.
	(xtensa_stateOperand_state, xtensa_stateOperand_inout,
	xtensa_interfaceOperand_interface, xtensa_regfile_lookup,
	xtensa_regfile_lookup_shortname, xtensa_regfile_name,
	xtensa_regfile_shortname, xtensa_regfile_view_parent,
	xtensa_regfile_num_bits, xtensa_regfile_num_entries,
	xtensa_state_lookup, xtensa_state_name, xtensa_state_num_bits,
	xtensa_state_is_exported, xtensa_sysreg_lookup,
	xtensa_sysreg_lookup_name, xtensa_sysreg_name, xtensa_sysreg_number,
	xtensa_sysreg_is_user, xtensa_interface_lookup, xtensa_interface_name,
	xtensa_interface_num_bits, xtensa_interface_inout,
	xtensa_interface_has_side_effect, xtensa_funcUnit_lookup,
	xtensa_funcUnit_name, xtensa_funcUnit_num_copies): New.
	* xtensa-modules.c: Rewrite to use new data structures.
	* reloc.c (BFD_RELOC_XTENSA_DIFF8, BFD_RELOC_XTENSA_DIFF16,
	BFD_RELOC_XTENSA_DIFF32, BFD_RELOC_XTENSA_SLOT0_OP,
	BFD_RELOC_XTENSA_SLOT1_OP, BFD_RELOC_XTENSA_SLOT2_OP,
	BFD_RELOC_XTENSA_SLOT3_OP, BFD_RELOC_XTENSA_SLOT4_OP,
	BFD_RELOC_XTENSA_SLOT5_OP, BFD_RELOC_XTENSA_SLOT6_OP,
	BFD_RELOC_XTENSA_SLOT7_OP, BFD_RELOC_XTENSA_SLOT8_OP,
	BFD_RELOC_XTENSA_SLOT9_OP, BFD_RELOC_XTENSA_SLOT10_OP,
	BFD_RELOC_XTENSA_SLOT11_OP, BFD_RELOC_XTENSA_SLOT12_OP,
	BFD_RELOC_XTENSA_SLOT13_OP, BFD_RELOC_XTENSA_SLOT14_OP,
	BFD_RELOC_XTENSA_SLOT0_ALT, BFD_RELOC_XTENSA_SLOT1_ALT,
	BFD_RELOC_XTENSA_SLOT2_ALT, BFD_RELOC_XTENSA_SLOT3_ALT,
	BFD_RELOC_XTENSA_SLOT4_ALT, BFD_RELOC_XTENSA_SLOT5_ALT,
	BFD_RELOC_XTENSA_SLOT6_ALT, BFD_RELOC_XTENSA_SLOT7_ALT,
	BFD_RELOC_XTENSA_SLOT8_ALT, BFD_RELOC_XTENSA_SLOT9_ALT,
	BFD_RELOC_XTENSA_SLOT10_ALT, BFD_RELOC_XTENSA_SLOT11_ALT,
	BFD_RELOC_XTENSA_SLOT12_ALT, BFD_RELOC_XTENSA_SLOT13_ALT,
	BFD_RELOC_XTENSA_SLOT14_ALT): Add new relocations.
	* Makefile.am (xtensa-isa.lo, xtensa-modules.lo): Update dependencies.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Likewise.
	* libbfd.h: Likewise.

gas ChangeLog

	* config/tc-xtensa.c (absolute_literals_supported): New global flag.
	(UNREACHABLE_MAX_WIDTH): Define.
	(XTENSA_FETCH_WIDTH): Delete.
	(cur_vinsn, xtensa_fetch_width, xt_saved_debug_type, past_xtensa_end,
	prefer_const16, prefer_l32r): New global variables.
	(LIT4_SECTION_NAME): Define.
	(lit4_state struct): Add lit4_seg_name and lit4_seg fields.
	(XTENSA_PROP_*, GET_XTENSA_PROP_*, SET_XTENSA_PROP_*): Define.
	(frag_flags struct): New.
	(xtensa_block_info struct): Move from tc-xtensa.h.  Add flags field.
	(subseg_map struct): Add cur_total_freq and cur_target_freq fields.
	(bitfield, bit_is_set, set_bit, clear_bit): Define.
	(MAX_FORMATS): Define.
	(op_placement_info struct, op_placement_table): New.
	(O_pltrel, O_hi16, O_lo16): Define.
	(directiveE enum): Rename directive_generics to directive_transform.
	Delete directive_relax.  Add directive_schedule,
	directive_absolute_literals, and directive_last_directive.
	(directive_info): Rename "generics" to "transform".  Delete "relax".
	Add "schedule" and "absolute-literals".
	(directive_state): Adjust entries to match changes in directive_info.
	(xtensa_relax_statesE, RELAX_IMMED_MAXSTEPS): Move to tc-xtensa.h.
	(xtensa_const16_opcode, xtensa_movi_opcode, xtensa_movi_n_opcode,
	xtensa_l32r_opcode, xtensa_nop_opcode, xtensa_rsr_lcount_opcode): New.
	(xtensa_j_opcode, xtensa_rsr_opcode): Delete.
	(align_only_targets, software_a0_b_retw_interlock,
	software_avoid_b_j_loop_end, maybe_has_b_j_loop_end,
	software_avoid_short_loop, software_avoid_close_loop_end,
	software_avoid_all_short_loops, specific_opcode): Delete.
	(warn_unaligned_branch_targets): New.
	(workaround_a0_b_retw, workaround_b_j_loop_end, workaround_short_loop,
	workaround_close_loop_end, workaround_all_short_loops): Default FALSE.
	(option_[no_]link_relax, option_[no_]transform,
	option_[no_]absolute_literals, option_warn_unaligned_targets,
	option_prefer_l32r, option_prefer_const16, option_target_hardware):
	New enum values.
	(option_[no_]align_only_targets, option_literal_section_name,
	option_text_section_name, option_data_section_name,
	option_bss_section_name, option_eb, option_el): Delete.
	(md_longopts): Add entries for: [no-]transform, [no-]absolute-literals,
	warn-unaligned-targets, prefer-l32r, prefer-const16, [no-]link-relax,
	and target-hardware.  Delete entries for [no-]target-align-only,
	literal-section-name, text-section-name, data-section-name, and
	bss-section-name.
	(md_parse_option): Handle new options and remove old ones.  Accept but
	ignore [no-]density options.  Warn for [no-]generics and [no-]relax
	and treat them as [no-]transform.
	(md_show_usage): Add new options and remove old ones.
	(xtensa_setup_hw_workarounds): New.
	(md_pseudo_table): Change "word" entry to use xtensa_elf_cons.  Add
	"long", "short", "loc" and "frequency" entries.
	(use_generics): Rename to ...
	(use_transform): ... this function.  Add past_xtensa_end check.
	(use_longcalls): Add past_xtensa_end check.
	(code_density_available, can_relax): Delete.
	(do_align_targets): New.
	(get_directive): Accept dashes in directive names.  Warn about
	[no-]generics and [no-]relax directives and treat them as
	[no-]transform.
	(xtensa_begin_directive): Call md_flush_pending_output only for some
	directives.  Check for directives inside instruction bundles.  Warn
	about deprecated ".begin literal" usage.  Warn and ignore [no-]density
	directives.  Handle new directives.  Check generating_literals flag
	for literal_prefix.
	(xtensa_end_directive): Check for directives inside instruction
	bundles.  Warn and ignore [no-]density directives.  Handle new
	directives.  Call xtensa_set_frag_assembly_state.
	(xtensa_loc_directive_seen, xtensa_dwarf2_directive_loc,
	xtensa_dwarf2_emit_insn): New.
	(xtensa_literal_position): Call md_flush_pending_output.  Do not check
	use_literal_section flag.
	(xtensa_literal_pseudo): Call md_flush_pending_output.  Handle absolute
	literals.  Use xtensa_elf_cons to parse the expression.
	(xtensa_literal_prefix): Do not check use_literal_section.  Support
	".lit4" sections for absolute literals.  Change prefix convention to
	replace ".text" (or ".t" in a linkonce section).  No need to call
	subseg_set.
	(xtensa_frequency_pseudo, xtensa_elf_cons, xtensa_elf_suffix): New.
	(expression_end): Handle closing braces and colons.
	(PLT_SUFFIX, plt_suffix): Delete.
	(expression_maybe_register): Use new xtensa-isa.h functions.  Use
	xtensa_elf_suffix instead of checking for plt suffix, and handle O_lo16
	and O_hi16 expressions as well.
	(tokenize_arguments): Handle closing braces and colons.
	(parse_arguments): Use new xtensa-isa.h functions.  Handle "invisible"
	operands and paired register syntax.
	(get_invisible_operands): New.
	(xg_translate_sysreg_op): Handle new Xtensa LX RSR/WSR/XSR syntax.  Use
	new xtensa-isa.h functions.
	(xtensa_translate_old_userreg_ops, xtensa_translate_zero_immed): New.
	(xg_translate_idioms): Check if inside bundle.  Use use_transform.
	Handle new Xtensa LX RSR/WSR/XSR syntax.  Remove code to widen density
	instructions.  Use xtensa_translate_zero_immed.
	(operand_is_immed, operand_is_pcrel_label): Delete.
	(get_relaxable_immed): Use new xtensa-isa.h functions.
	(get_opcode_from_buf): Add slot parameter.  Use new xtensa-isa.h
	functions.
	(xtensa_print_insn_table, print_vliw_insn): New.
	(is_direct_call_opcode): Use new xtensa-isa.h functions.
	(is_call_opcode, is_loop_opcode, is_conditional_branch_opcode,
	is_branch_or_jump_opcode): Delete.
	(is_movi_opcode, decode_reloc, encode_reloc, encode_alt_reloc): New.
	(opnum_to_reloc, reloc_to_opnum): Delete.
	(xtensa_insnbuf_set_operand, xtensa_insnbuf_get_operand): Use new
	xtensa-isa.h functions.  Operate on one slot of an instruction.
	(xtensa_insnbuf_set_immediate_field, is_negatable_branch,
	xg_get_insn_size): Delete.
	(xg_get_build_instr_size): Use xg_get_single_size.
	(xg_is_narrow_insn, xg_is_single_relaxable_insn): Update calls to
	xg_build_widen_table.  Use xg_get_single_size.
	(xg_get_max_narrow_insn_size): Delete.
	(xg_get_max_insn_widen_size, xg_get_max_insn_widen_literal_size,
	xg_is_relaxable_insn): Update calls to xg_build_widen_table.  Use
	xg_get_single_size.
	(xg_build_to_insn): Record the loc field.  Handle OP_OPERAND_HI16U and
	OP_OPERAND_LOW16U.  Check xg_valid_literal_expression.
	(xg_expand_to_stack, xg_expand_narrow): Update calls to
	xg_build_widen_table.  Use xg_get_single_size.
	(xg_immeds_fit): Use new xtensa-isa.h functions.  Update call to
	xg_check_operand.
	(xg_symbolic_immeds_fit): Likewise.  Also handle O_lo16 and O_hi16, and
	treat weak symbols conservatively.
	(xg_check_operand): Use new xtensa-isa.h functions.
	(is_dnrange): Delete.
	(xg_assembly_relax): Inline previous calls to tinsn_copy.
	(xg_finish_frag): Specify separate relax states for the frag and slot0.
	(is_branch_jmp_to_next, xg_add_branch_and_loop_targets): Use new
	xtensa-isa.h functions.
	(xg_instruction_matches_option_term, xg_instruction_matches_or_options,
	xg_instruction_matches_options): New.
	(xg_instruction_matches_rule): Handle O_register expressions.  Call
	xg_instruction_matches_options.
	(transition_rule_cmp): New.
	(xg_instruction_match): Update call to xg_build_simplify_table.
	(xg_build_token_insn): Record loc fields.
	(xg_simplify_insn): Check is_specific_opcode field and
	density_supported flag.
	(xg_expand_assembly_insn): Skip checking code_density_available.  Use
	new xtensa-isa.h functions.  Call use_transform instead of can_relax.
	(xg_assemble_literal): Add error handling for O_big.  Call
	record_alignment.  Handle O_pltrel.
	(xg_valid_literal_expression): New.
	(xg_assemble_literal_space): Add slot parameter.  Remove call to
	set_expr_symbol_offset.  Add call to record_alignment.  Update call to
	xg_finish_frag.
	(xg_emit_insn): Delete.
	(xg_emit_insn_to_buf): Add format parameter.  Update calls to
	xg_add_opcode_fix and xtensa_insnbuf_to_chars.
	(xg_add_opcode_fix): Change opcode parameter to tinsn and add format
	and slot parameters.  Handle new "alternate" relocations for absolute
	literals and CONST16 instructions.  Check for bad uses of O_lo16 and
	O_hi16.  Use new xtensa-isa.h functions.
	(xg_assemble_tokens): Delete.
	(is_register_writer): Use new xtensa-isa.h functions.
	(is_bad_loopend_opcode): Check for xtensa_rsr_lcount_opcode instead of
	old-style RSR from LCOUNT.
	(next_frag_opcode): Delete.
	(next_frag_opcode_is_loop, next_frag_format_size, frag_format_size,
	update_next_frag_state): New.
	(update_next_frag_nop_state): Delete.
	(next_frag_pre_opcode_bytes): Use next_frag_opcode_is_loop.
	(xtensa_mark_literal_pool_location): Check use_literal_section flag and
	the state of the absolute-literals directive.  Add calls to
	record_alignment and xtensa_set_frag_assembly_state.  Call
	xtensa_switch_to_non_abs_literal_fragment instead of
	xtensa_switch_to_literal_fragment.
	(build_nop): New.
	(assemble_nop): Use build_nop.  Update call to xtensa_insnbuf_to_chars.
	(get_expanded_loop_offset): Change check for undefined opcode to an
	assertion.
	(xtensa_set_frag_assembly_state, relaxable_section,
	xtensa_find_unmarked_state_frags, xtensa_find_unaligned_branch_targets,
	xtensa_find_unaligned_loops, xg_apply_tentative_value): New.
	(md_begin): Update call to xtensa_isa_init.  Initialize linkrelax to 1.
	Set lit4_seg_name.  Call xg_init_vinsn.  Initialize new global opcodes.
	Call init_op_placement_info_table and xtensa_set_frag_assembly_state.
	(xtensa_init_fix_data): New.
	(xtensa_frob_label): Reset label symbol to the current frag.  Check
	do_align_targets and generating_literals flag.  Propagate frequency
	info to new alignment frag.  Call xtensa_set_frag_assembly_state.
	(xtensa_unrecognized_line): New.
	(xtensa_flush_pending_output): Check if inside a bundle.  Add a call
	to xtensa_set_frag_assembly_state.
	(error_reset_cur_vinsn): New.
	(md_assemble): Remove check for literal frag.  Remove call to
	istack_init.  Call use_transform instead of use_generics.  Parse
	explicit instruction format specifiers.  Move code for
	a0_b_retw_interlock workaround to xg_assemble_vliw_tokens.  Call
	error_reset_cur_vinsn on errors.  Add call to get_invisible_operands.
	Add dwarf2_where call.  Remote automatic alignment for ENTRY
	instructions.  Move call to xtensa_clear_insn_labels to the end.
	Rearrange to handle bundles.
	(xtensa_cons_fix_new): Delete.
	(xtensa_handle_align): New.
	(xtensa_frag_init): Call xtensa_set_frag_assembly_state.  Remove
	assignment to is_no_density field.
	(md_pcrel_from): Use new xtensa-isa.h functions.  Use decode_reloc
	instead of reloc_to_opnum.  Handle "alternate" relocations.
	(xtensa_force_relocation, xtensa_check_inside_bundle,
	xtensa_elf_section_change_hook): New.
	(xtensa_symbol_new_hook): Delete.
	(xtensa_fix_adjustable): Check for difference of symbols with an
	offset.  Check for external and weak symbols.
	(md_apply_fix3): Remove cases for XTENSA_OP{0,1,2} relocs.
	(md_estimate_size_before_relax): Return expansion for the first slot.
	(tc_gen_reloc): Handle difference of symbols by producing
	XTENSA_DIFF{8,16,32} relocs and by writing the value of the difference
	into the output.  Handle new XTENSA_SLOT*_OP relocs by storing the
	tentative values into the output when linkrelax is set.
	(XTENSA_PROP_SEC_NAME): Define.
	(xtensa_post_relax_hook): Call xtensa_find_unmarked_state_frags.
	Create literal tables only if using literal sections.  Create new
	property tables instead of old instruction tables.  Check for unaligned
	branch targets and loops.
	(finish_vinsn, find_vinsn_conflicts, check_t1_t2_reads_and_writes,
	new_resource_table, clear_resource_table, resize_resource_table,
	resources_available, reserve_resources, release_resources,
	opcode_funcUnit_use_unit, opcode_funcUnit_use_stage,
	resources_conflict, xg_find_narrowest_format, relaxation_requirements,
	bundle_single_op, emit_single_op, xg_assemble_vliw_tokens): New.
	(xtensa_end): Call xtensa_flush_pending_output.  Set past_xtensa_end
	flag.  Update checks for workaround options.  Call
	xtensa_mark_narrow_branches and xtensa_mark_zcl_first_insns.
	(xtensa_cleanup_align_frags): Add special case for branch targets.
	Check for and mark unreachable frags.
	(xtensa_fix_target_frags): Remove use of align_only_targets flag.
	Use RELAX_LOOP_END_BYTES in special case for negatable branch at the
	end of a zero-overhead loop body.
	(frag_can_negate_branch): Handle instructions with multiple slots.
	Use new xtensa-isa.h functions
	(xtensa_mark_narrow_branches, is_narrow_branch_guaranteed_in_range,
	xtensa_mark_zcl_first_insns): New.
	(xtensa_fix_a0_b_retw_frags, xtensa_fix_b_j_loop_end_frags): Error if
	transformations are disabled.
	(next_instrs_are_b_retw): Use new xtensa-isa.h functions.  Handle
	multislot instructions.
	(xtensa_fix_close_loop_end_frags, xtensa_fix_short_loop_frags):
	Likewise.  Also error if transformations are disabled.
	(unrelaxed_frag_max_size): New.
	(unrelaxed_frag_min_insn_count, unrelax_frag_has_b_j): Use new
	xtensa-isa.h functions.
	(xtensa_sanity_check, is_empty_loop, is_local_forward_loop): Use
	xtensa_opcode_is_loop instead of is_loop_opcode.
	(get_text_align_power): Replace as_fatal with assertion.
	(get_text_align_fill_size): Iterate instead of using modulus when
	use_nops is false.
	(get_noop_aligned_address): Assert that this is for a machine-dependent
	RELAX_ALIGN_NEXT_OPCODE frag.  Use next_frag_opcode_is_loop,
	xg_get_single_size, and frag_format_size.
	(get_widen_aligned_address): Rename to ...
	(get_aligned_diff): ... this function.  Add max_diff parameter.
	Remove handling of rs_align/rs_align_code frags.  Use
	next_frag_format_size, get_text_align_power, get_text_align_fill_size,
	next_frag_opcode_is_loop, and xg_get_single_size.  Compute max_diff
	and pass it back to caller.
	(xtensa_relax_frag): Use relax_frag_loop_align.  Add code for new
	RELAX_SLOTS, RELAX_MAYBE_UNREACHABLE, RELAX_MAYBE_DESIRE_ALIGN,
	RELAX_FILL_NOP, and RELAX_UNREACHABLE frag types.  Check relax_seen.
	(relax_frag_text_align): Rename to ...
	(relax_frag_loop_align): ... this function.  Assume loops can only be
	in the first slot of an instruction.
	(relax_frag_add_nop): Use assemble_nop instead of constructing an OR
	instruction.  Remove call to frag_wane.
	(relax_frag_narrow): Rename to ...
	(relax_frag_for_align): ... this function.  Extend to handle
	RELAX_FILL_NOP and RELAX_UNREACHABLE, as well as RELAX_SLOTS with
	RELAX_NARROW for the first slot.
	(find_address_of_next_align_frag, bytes_to_stretch): New.
	(future_alignment_required): Use find_address_of_next_align_frag and
	bytes_to_stretch.  Look ahead to subsequent frags to make smarter
	alignment decisions.
	(relax_frag_immed): Add format, slot, and estimate_only parameters.
	Check if transformations are enabled for b_j_loop_end workaround.
	Use new xtensa-isa.h functions and handle multislot instructions.
	Update call to xg_assembly_relax.
	(md_convert_frag): Handle new RELAX_SLOTS, RELAX_UNREACHABLE,
	RELAX_MAYBE_UNREACHABLE, RELAX_MAYBE_DESIRE_ALIGN, and RELAX_FILL_NOP
	frag types.
	(convert_frag_narrow): Add segP, format and slot parameters.  Call
	convert_frag_immed for branch instructions.  Adjust calls to
	tinsn_from_chars, tinsn_immed_from_frag, and xg_emit_insn_to_buf.  Use
	xg_get_single_size and xg_get_single_format.
	(convert_frag_fill_nop): New.
	(convert_frag_immed): Add format and slot parameters.  Handle multislot
	instructions and use new xtensa-isa.h functions.  Update calls to
	tinsn_immed_from_frag and xg_assembly_relax.  Check if transformations
	enabled for b_j_loop_end workaround.  Use build_nop instead of
	assemble_nop.  Check is_specific_opcode flag.  Check for unreachable
	frags.  Use xg_get_single_size.  Handle O_pltrel.
	(fix_new_exp_in_seg): Remove check for old plt flag.
	(convert_frag_immed_finish_loop): Update calls to tinsn_from_chars and
	xtensa_insnbuf_to_chars.  Call tinsn_immed_from_frag.  Change check
	for loop opcode to an assertion.  Mark all frags up to the end of the
	loop as not transformable.
	(get_last_insn_flags, set_last_insn_flags): Use get_subseg_info.
	(get_subseg_info): New.
	(xtensa_move_literals): Call xtensa_set_frag_assembly_state.  Add null
	check for dest_seg.
	(xtensa_switch_to_literal_fragment): Rewrite to handle absolute
	literals and use xtensa_switch_to_non_abs_literal_fragment otherwise.
	(xtensa_switch_to_non_abs_literal_fragment): New.
	(cache_literal_section): Add is_code parameter and pass it through to
	retrieve_literal_seg.
	(retrieve_literal_seg): Add is_code parameter and use it to set the
	flags on the literal section.  Handle case where head parameter is 0.
	(get_frag_is_no_transform, set_frag_is_specific_opcode,
	set_frag_is_no_transform): New.
	(xtensa_create_property_segments): Add end_property_function parameter
	and pass it through to add_xt_block_frags.  Call bfd_get_section_flags
	and skip SEC_DEBUGGING and !SEC_ALLOC sections.
	(xtensa_create_xproperty_segments, section_has_xproperty): New.
	(add_xt_block_frags): Add end_property_function parameter and call it
	if it is non-zero.  Call xtensa_frag_flags_init.
	(xtensa_frag_flags_is_empty, xtensa_frag_flags_init,
	get_frag_property_flags, frag_flags_to_number,
	xtensa_frag_flags_combinable, xt_block_aligned_size,
	xtensa_xt_block_combine, add_xt_prop_frags,
	init_op_placement_info_table, opcode_fits_format_slot,
	xg_get_single_size, xg_get_single_format): New.
	(istack_push): Inline call to tinsn_copy.
	(tinsn_copy): Delete.
	(tinsn_has_invalid_symbolic_operands): Handle O_hi16 and O_lo16 and
	CONST16 opcodes.  Handle O_big, O_illegal, and O_absent.
	(tinsn_has_complex_operands): Handle O_hi16 and O_lo16.
	(tinsn_to_insnbuf): Use xg_get_single_format and new xtensa-isa.h
	functions.  Handle invisible operands.
	(tinsn_to_slotbuf): New.
	(tinsn_check_arguments): Use new xtensa-isa.h functions.
	(tinsn_from_chars): Add slot parameter.  Rewrite using xg_init_vinsn,
	vinsn_from_chars, and xg_free_vinsn.
	(tinsn_from_insnbuf): New.
	(tinsn_immed_from_frag): Add slot parameter and handle multislot
	instructions.  Handle symbol differences.
	(get_num_stack_text_bytes): Use xg_get_single_size.
	(xg_init_vinsn, xg_clear_vinsn, vinsn_has_specific_opcodes,
	xg_free_vinsn, vinsn_to_insnbuf, vinsn_from_chars, expr_is_register,
	get_expr_register, set_expr_symbol_offset_diff): New.
	* config/tc-xtensa.h (MAX_SLOTS): Define.
	(xtensa_relax_statesE): Move from tc-xtensa.c. Add
	RELAX_CHECK_ALIGN_NEXT_OPCODE, RELAX_MAYBE_DESIRE_ALIGN, RELAX_SLOTS,
	RELAX_FILL_NOP, RELAX_UNREACHABLE, RELAX_MAYBE_UNREACHABLE, and
	RELAX_NONE types.
	(RELAX_IMMED_MAXSTEPS): Move from tc-xtensa.c.
	(xtensa_frag_type struct): Add is_assembly_state_set,
	use_absolute_literals, relax_seen, is_unreachable, is_specific_opcode,
	is_align, is_text_align, alignment, and is_first_loop_insn fields.
	Replace is_generics and is_relax fields by is_no_transform field.
	Delete is_text and is_longcalls fields.  Change text_expansion and
	literal_expansion to arrays of MAX_SLOTS entries.  Add arrays of
	per-slot information: literal_frags, slot_subtypes, slot_symbols,
	slot_sub_symbols, and slot_offsets.  Add fr_prev field.
	(xtensa_fix_data struct): New.
	(xtensa_symfield_type struct): Delete plt field.
	(xtensa_block_info struct): Move definition to tc-xtensa.h.  Add
	forward declaration here.
	(xt_section_type enum): Delete xt_insn_sec.  Add xt_prop_sec.
	(XTENSA_SECTION_RENAME): Undefine.
	(TC_FIX_TYPE, TC_INIT_FIX_DATA, TC_FORCE_RELOCATION, NO_PSEUDO_DOT,
	tc_unrecognized_line, md_do_align, md_elf_section_change_hook,
	HANDLE_ALIGN, TC_LINKRELAX_FIXUP, SUB_SEGMENT_ALIGN): Define.
	(TC_CONS_FIX_NEW, tc_symbol_new_hook): Delete.
	(unit_num_copies_func, opcode_num_units_func,
	opcode_funcUnit_use_unit_func, opcode_funcUnit_use_stage_func): New.
	(resource_table struct): New.
	* config/xtensa-istack.h (MAX_INSN_ARGS): Increase from 6 to 10.
	(TInsn struct): Add keep_wide, loc, fixup, record_fix, subtype,
	literal_space, symbol, sub_symbol, offset, and literal_frag fields.
	(tinsn_copy): Delete prototype.
	(vliw_insn struct): New.
	* config/xtensa-relax.c (insn_pattern_struct): Add options field.
	(widen_spec_list): Add option conditions for density and boolean
	instructions.  Add expansions using CONST16 and conditions for using
	CONST16 vs. L32R.  Use new Xtensa LX RSR/WSR syntax.  Add entries for
	predicted branches.
	(simplify_spec_list): Add option conditions for density instructions.
	Add entry for NOP instruction.
	(append_transition): Add cmp function pointer parameter and use it to
	insert the new entry in order.
	(operand_function_LOW16U, operand_function_HI16U): New.
	(xg_has_userdef_op_fn, xg_apply_userdef_op_fn): Handle
	OP_OPERAND_LOW16U and OP_OPERAND_HI16U.
	(enter_opname, split_string): Use xstrdup instead of strdup.
	(init_insn_pattern): Initialize new options field.
	(clear_req_or_option_list, clear_req_option_list,
	clone_req_or_option_list, clone_req_option_list, parse_option_cond):
	New.
	(parse_insn_pattern): Parse option conditions.
	(transition_applies): New.
	(build_transition): Use new xtensa-isa.h functions.  Fix incorrectly
	swapped last arguments in calls to append_constant_value_condition.
	Call clone_req_option_list.  Add warning about invalid opcode.
	Handle LOW16U and HI16U function names.
	(build_transition_table): Add cmp parameter and use it in calls to
	append_transition.  Use new xtensa-isa.h functions.  Check
	transition_applies before adding entries.
	(xg_build_widen_table, xg_build_simplify_table): Add cmp parameter and
	pass it through to build_transition_table.
	* config/xtensa-relax.h (ReqOrOptionList, ReqOrOption, ReqOptionList,
	ReqOption, transition_cmp_fn): New types.
	(OpType enum): Add OP_OPERAND_LOW16U and OP_OPERAND_HI16U.
	(transition_rule struct): Add options field.
	* doc/as.texinfo (Overview): Update Xtensa options.
	* doc/c-xtensa.texi (Xtensa Options): Delete --[no-]density,
	--[no-]relax, and --[no-]generics options.  Update descriptions of
	--text-section-literals and --[no-]longcalls.  Add
	--[no-]absolute-literals and --[no-]transform.
	(Xtensa Syntax): Add description of syntax for FLIX instructions.
	Remove use of "generic" and "specific" terminology for opcodes.
	(Xtensa Registers): Generalize the syntax description to include
	user-defined register files.
	(Xtensa Automatic Alignment): Update.
	(Xtensa Branch Relaxation): Mention limitation of unconditional jumps.
	(Xtensa Call Relaxation): Linker can now remove most of the overhead.
	(Xtensa Directives): Remove confusing rules about precedence.
	(Density Directive, Relax Directive): Delete.
	(Schedule Directive): New.
	(Generics Directive): Rename to ...
	(Transform Directive): ... this node.
	(Literal Directive): Update for absolute literals.  Missing
	literal_position directive is now an error.
	(Literal Position Directive): Update for absolute literals.
	(Freeregs Directive): Delete.
	(Absolute Literals Directive): New.
	(Frame Directive): Minor editing.
	* Makefile.am (DEPTC_xtensa_elf, DEPOBJ_xtensa_elf, DEP_xtensa_elf):
	Update dependencies.
	* Makefile.in: Regenerate.

gas/testsuite ChangeLog

	* gas/xtensa/all.exp: Adjust expected error message for j_too_far.
	Change entry_align test to expect an error.
	* gas/xtensa/entry_misalign2.s: Use no-transform instead of
	no-generics directives.

include ChangeLog

	* xtensa-config.h (XSHAL_USE_ABSOLUTE_LITERALS,
	XCHAL_HAVE_PREDICTED_BRANCHES, XCHAL_INST_FETCH_WIDTH): New.
	(XCHAL_EXTRA_SA_SIZE, XCHAL_EXTRA_SA_ALIGN): Delete.
	* xtensa-isa-internal.h (ISA_INTERFACE_VERSION): Delete.
	(config_sturct struct): Delete.
	(XTENSA_OPERAND_IS_REGISTER, XTENSA_OPERAND_IS_PCRELATIVE,
	XTENSA_OPERAND_IS_INVISIBLE, XTENSA_OPERAND_IS_UNKNOWN,
	XTENSA_OPCODE_IS_BRANCH, XTENSA_OPCODE_IS_JUMP,
	XTENSA_OPCODE_IS_LOOP, XTENSA_OPCODE_IS_CALL,
	XTENSA_STATE_IS_EXPORTED, XTENSA_INTERFACE_HAS_SIDE_EFFECT): Define.
	(xtensa_format_encode_fn, xtensa_get_slot_fn, xtensa_set_slot_fn): New.
	(xtensa_insn_decode_fn): Rename to ...
	(xtensa_opcode_decode_fn): ... this.
	(xtensa_immed_decode_fn, xtensa_immed_encode_fn, xtensa_do_reloc_fn,
	xtensa_undo_reloc_fn): Update.
	(xtensa_encoding_template_fn): Delete.
	(xtensa_opcode_encode_fn, xtensa_format_decode_fn,
	xtensa_length_decode_fn): New.
	(xtensa_format_internal, xtensa_slot_internal): New types.
	(xtensa_operand_internal): Delete operand_kind, inout, isPCRelative,
	get_field, and set_field fields.  Add name, field_id, regfile,
	num_regs, and flags fields.
	(xtensa_arg_internal): New type.
	(xtensa_iclass_internal): Change operands field to array of
	xtensa_arg_internal.  Add num_stateOperands, stateOperands,
	num_interfaceOperands, and interfaceOperands fields.
	(xtensa_opcode_internal): Delete length, template, and iclass fields.
	Add iclass_id, flags, encode_fns, num_funcUnit_uses, and funcUnit_uses.
	(opname_lookup_entry): Delete.
	(xtensa_regfile_internal, xtensa_interface_internal,
	xtensa_funcUnit_internal, xtensa_state_internal,
	xtensa_sysreg_internal, xtensa_lookup_entry): New.
	(xtensa_isa_internal): Replace opcode_table field with opcodes field.
	Change type of opname_lookup_table.  Delete num_modules,
	module_opcode_base, module_decode_fn, config, and has_density fields.
	Add num_formats, formats, format_decode_fn, length_decode_fn,
	num_slots, slots, num_fields, num_operands, operands, num_iclasses,
	iclasses, num_regfiles, regfiles, num_states, states,
	state_lookup_table, num_sysregs, sysregs, sysreg_lookup_table,
	max_sysreg_num, sysreg_table, num_interfaces, interfaces,
	interface_lookup_table, num_funcUnits, funcUnits and
	funcUnit_lookup_table fields.
	(xtensa_isa_module, xtensa_isa_modules): Delete.
	(xtensa_isa_name_compare): New prototype.
	(xtisa_errno, xtisa_error_msg): New.
	* xtensa-isa.h (XTENSA_ISA_VERSION): Define.
	(xtensa_isa): Change type.
	(xtensa_operand): Delete.
	(xtensa_format, xtensa_regfile, xtensa_state, xtensa_sysreg,
	xtensa_interface, xtensa_funcUnit, xtensa_isa_status,
	xtensa_funcUnit_use): New types.
	(libisa_module_specifier): Delete.
	(xtensa_isa_errno, xtensa_isa_error_msg): New prototypes.
	(xtensa_insnbuf_free, xtensa_insnbuf_to_chars,
	xtensa_insnbuf_from_chars): Update prototypes.
	(xtensa_load_isa, xtensa_extend_isa, xtensa_default_isa,
	xtensa_insn_maxlength, xtensa_num_opcodes, xtensa_decode_insn,
	xtensa_encode_insn, xtensa_insn_length,
	xtensa_insn_length_from_first_byte, xtensa_num_operands,
	xtensa_operand_kind, xtensa_encode_result,
	xtensa_operand_isPCRelative): Delete.
	(xtensa_isa_init, xtensa_operand_inout, xtensa_operand_get_field,
	xtensa_operand_set_field, xtensa_operand_encode,
	xtensa_operand_decode, xtensa_operand_do_reloc,
	xtensa_operand_undo_reloc): Update prototypes.
	(xtensa_isa_maxlength, xtensa_isa_length_from_chars,
	xtensa_isa_num_pipe_stages, xtensa_isa_num_formats,
	xtensa_isa_num_opcodes, xtensa_isa_num_regfiles, xtensa_isa_num_states,
	xtensa_isa_num_sysregs, xtensa_isa_num_interfaces,
	xtensa_isa_num_funcUnits, xtensa_format_name, xtensa_format_lookup,
	xtensa_format_decode, xtensa_format_encode, xtensa_format_length,
	xtensa_format_num_slots, xtensa_format_slot_nop_opcode,
	xtensa_format_get_slot, xtensa_format_set_slot, xtensa_opcode_decode,
	xtensa_opcode_encode, xtensa_opcode_is_branch, xtensa_opcode_is_jump,
	xtensa_opcode_is_loop, xtensa_opcode_is_call,
	xtensa_opcode_num_operands, xtensa_opcode_num_stateOperands,
	xtensa_opcode_num_interfaceOperands, xtensa_opcode_num_funcUnit_uses,
	xtensa_opcode_funcUnit_use, xtensa_operand_name,
	xtensa_operand_is_visible, xtensa_operand_is_register,
	xtensa_operand_regfile, xtensa_operand_num_regs,
	xtensa_operand_is_known_reg, xtensa_operand_is_PCrelative,
	xtensa_stateOperand_state, xtensa_stateOperand_inout,
	xtensa_interfaceOperand_interface, xtensa_regfile_lookup,
	xtensa_regfile_lookup_shortname, xtensa_regfile_name,
	xtensa_regfile_shortname, xtensa_regfile_view_parent,
	xtensa_regfile_num_bits, xtensa_regfile_num_entries,
	xtensa_state_lookup, xtensa_state_name, xtensa_state_num_bits,
	xtensa_state_is_exported, xtensa_sysreg_lookup,
	xtensa_sysreg_lookup_name, xtensa_sysreg_name, xtensa_sysreg_number,
	xtensa_sysreg_is_user, xtensa_interface_lookup, xtensa_interface_name,
	xtensa_interface_num_bits, xtensa_interface_inout,
	xtensa_interface_has_side_effect, xtensa_funcUnit_lookup,
	xtensa_funcUnit_name, xtensa_funcUnit_num_copies): New prototypes.
	* elf/xtensa.h (R_XTENSA_DIFF8, R_XTENSA_DIFF16, R_XTENSA_DIFF32,
	R_XTENSA_SLOT*_OP, R_XTENSA_SLOT*_ALT): New relocations.
	(XTENSA_PROP_SEC_NAME): Define.
	(property_table_entry): Add flags field.
	(XTENSA_PROP_*, GET_XTENSA_PROP_*, SET_XTENSA_PROP_*): Define.

ld ChangeLog

	* ld.texinfo (Xtensa): Describe new linker relaxation to optimize
	assembler-generated longcall sequences.  Describe new --size-opt
	option.
	* emulparams/elf32xtensa.sh (OTHER_SECTIONS): Add .xt.prop section.
	* emultempl/xtensaelf.em (remove_section,
	replace_insn_sec_with_prop_sec, replace_instruction_table_sections,
	elf_xtensa_after_open): New.
	(OPTION_OPT_SIZEOPT, OPTION_LITERAL_MOVEMENT,
	OPTION_NO_LITERAL_MOVEMENT): Define.
	(elf32xtensa_size_opt, elf32xtensa_no_literal_movement): New globals.
	(PARSE_AND_LIST_LONGOPTS): Add size-opt and [no-]literal-movement.
	(PARSE_AND_LIST_OPTIONS): Add --size-opt.
	(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_OPT_SIZEOPT,
	OPTION_LITERAL_MOVEMENT, and OPTION_NO_LITERAL_MOVEMENT.
	(LDEMUL_AFTER_OPEN): Set to elf_xtensa_after_open.
	* scripttempl/elfxtensa.sc: Update with changes from elf.sc.
	* Makefile.am (eelf32xtensa.c): Update dependencies.
	* Makefile.in: Regenerate.

ld/testsuite ChangeLog

	* ld-xtensa/lcall1.s: Use .literal directive.
	* ld-xtensa/lcall2.s: Align function entry.
	* ld-xtensa/coalesce2.s: Likewise.

opcodes ChangeLog

	* xtensa-dis.c (state_names): Delete.
	(fetch_data): Use xtensa_isa_maxlength.
	(print_xtensa_operand): Replace operand parameter with opcode/operand
	pair.  Remove print_sr_name parameter.  Use new xtensa-isa.h functions.
	(print_insn_xtensa): Use new xtensa-isa.h functions.  Handle multislot
	instruction bundles.  Use xmalloc instead of malloc.

2 files changed, 257 insertions, 232 deletions

diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index 23de55f..0ede21a 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -420,9 +420,9 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
 @ifset XTENSA
 
 @emph{Target Xtensa options:}
- [@b{--[no-]density}] [@b{--[no-]relax}] [@b{--[no-]generics}]
- [@b{--[no-]text-section-literals}]
+ [@b{--[no-]text-section-literals}] [@b{--[no-]absolute-literals}]
  [@b{--[no-]target-align}] [@b{--[no-]longcalls}]
+ [@b{--[no-]transform}]
 @end ifset
 @c man end
 @end smallexample
@@ -1061,28 +1061,19 @@ The following options are available when @value{AS} is configured for
 an Xtensa processor.
 
 @table @gcctabopt
-@item --density | --no-density
-Enable or disable use of instructions from the Xtensa code density
-option.  This is enabled by default when the Xtensa processor supports
-the code density option.
-
-@item --relax | --no-relax
-Enable or disable instruction relaxation.  This is enabled by default.
-Note: In the current implementation, these options also control whether
-assembler optimizations are performed, making these options equivalent
-to @option{--generics} and @option{--no-generics}.
-
-@item --generics | --no-generics
-Enable or disable all assembler transformations of Xtensa instructions.
-The default is @option{--generics};
-@option{--no-generics} should be used only in the rare cases when the
-instructions must be exactly as specified in the assembly source.
-
 @item --text-section-literals | --no-text-section-literals
 With @option{--text-@-section-@-literals}, literal pools are interspersed
 in the text section.  The default is
 @option{--no-@-text-@-section-@-literals}, which places literals in a
-separate section in the output file.
+separate section in the output file.  These options only affect literals
+referenced via PC-relative @code{L32R} instructions; literals for
+absolute mode @code{L32R} instructions are handled separately.
+
+@item --absolute-literals | --no-absolute-literals
+Indicate to the assembler whether @code{L32R} instructions use absolute
+or PC-relative addressing.  The default is to assume absolute addressing
+if the Xtensa processor includes the absolute @code{L32R} addressing
+option.  Otherwise, only the PC-relative @code{L32R} mode can be used.
 
 @item --target-align | --no-target-align
 Enable or disable automatic alignment to reduce branch penalties at the
@@ -1092,6 +1083,12 @@ expense of some code density.  The default is @option{--target-@-align}.
 Enable or disable transformation of call instructions to allow calls
 across a greater range of addresses.  The default is
 @option{--no-@-longcalls}.
+
+@item --transform | --no-transform
+Enable or disable all assembler transformations of Xtensa instructions.
+The default is @option{--transform};
+@option{--no-transform} should be used only in the rare cases when the
+instructions must be exactly as specified in the assembly source.
 @end table
 @end ifset
 
diff --git a/gas/doc/c-xtensa.texi b/gas/doc/c-xtensa.texi
index 5e5f13a..5101d31 100644
--- a/gas/doc/c-xtensa.texi
+++ b/gas/doc/c-xtensa.texi
@@ -1,4 +1,4 @@
-@c Copyright (C) 2002 Free Software Foundation, Inc.
+@c Copyright (C) 2002, 2004 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @c
@@ -33,54 +33,30 @@ The Xtensa version of the @sc{gnu} assembler supports these
 special options:
 
 @table @code
-@item --density | --no-density
-@kindex --density
-@kindex --no-density
-@cindex Xtensa density option
-@cindex density option, Xtensa
-Enable or disable use of the Xtensa code density option (16-bit
-instructions).  @xref{Density Instructions, ,Using Density
-Instructions}.  If the processor is configured with the density option,
-this is enabled by default; otherwise, it is always disabled.
-
-@item --relax | --no-relax
-@kindex --relax
-@kindex --no-relax
-Enable or disable relaxation of instructions with immediate operands
-that are outside the legal range for the instructions.  @xref{Xtensa
-Relaxation, ,Xtensa Relaxation}.  The default is @samp{--relax} and this
-default should almost always be used.  If relaxation is disabled with
-@samp{--no-relax}, instruction operands that are out of range will cause
-errors.  Note: In the current implementation, these options also control
-whether assembler optimizations are performed, making these options
-equivalent to @samp{--generics} and @samp{--no-generics}.
-
-@item --generics | --no-generics
-@kindex --generics
-@kindex --no-generics
-Enable or disable all assembler transformations of Xtensa instructions,
-including both relaxation and optimization.  The default is
-@samp{--generics}; @samp{--no-generics} should only be used in the rare
-cases when the instructions must be exactly as specified in the assembly
-source.
-@c The @samp{--no-generics} option is like @samp{--no-relax}
-@c except that it also disables assembler optimizations (@pxref{Xtensa
-@c Optimizations}).
-As with @samp{--no-relax}, using @samp{--no-generics}
-causes out of range instruction operands to be errors.
-
 @item --text-section-literals | --no-text-section-literals
 @kindex --text-section-literals
 @kindex --no-text-section-literals
 Control the treatment of literal pools.  The default is
 @samp{--no-@-text-@-section-@-literals}, which places literals in a
 separate section in the output file.  This allows the literal pool to be
-placed in a data RAM/ROM, and it also allows the linker to combine literal
-pools from separate object files to remove redundant literals and
-improve code size.  With @samp{--text-@-section-@-literals}, the
+placed in a data RAM/ROM.  With @samp{--text-@-section-@-literals}, the
 literals are interspersed in the text section in order to keep them as
 close as possible to their references.  This may be necessary for large
-assembly files.
+assembly files, where the literals would otherwise be out of range of the
+@code{L32R} instructions in the text section.  These options only affect
+literals referenced via PC-relative @code{L32R} instructions; literals
+for absolute mode @code{L32R} instructions are handled separately.
+
+@item --absolute-literals | --no-absolute-literals
+@kindex --absolute-literals
+@kindex --no-absolute-literals
+Indicate to the assembler whether @code{L32R} instructions use absolute
+or PC-relative addressing.  If the processor includes the absolute
+addressing option, the default is to use absolute @code{L32R}
+relocations.  Otherwise, only the PC-relative @code{L32R} relocations
+can be used.  Literals referenced with absolute @code{L32R} relocations
+are always placed in the @code{.lit4} section, independent of the
+placement of PC-relative literals.
 
 @item --target-align | --no-target-align
 @kindex --target-align
@@ -97,14 +73,27 @@ have fixed alignment requirements.
 Enable or disable transformation of call instructions to allow calls
 across a greater range of addresses.  @xref{Xtensa Call Relaxation,
 ,Function Call Relaxation}.  This option should be used when call
-targets can potentially be out of range, but it degrades both code size
-and performance.  The default is @samp{--no-@-longcalls}.
+targets can potentially be out of range.  It may degrade both code size
+and performance, but the linker can generally optimize away the
+unnecessary overhead when a call ends up within range.  The default is
+@samp{--no-@-longcalls}.
+
+@item --transform | --no-transform
+@kindex --transform
+@kindex --no-transform
+Enable or disable all assembler transformations of Xtensa instructions,
+including both relaxation and optimization.  The default is
+@samp{--transform}; @samp{--no-transform} should only be used in the
+rare cases when the instructions must be exactly as specified in the
+assembly source.  Using @samp{--no-transform} causes out of range
+instruction operands to be errors.
 @end table
 
 @node Xtensa Syntax
 @section Assembler Syntax
 @cindex syntax, Xtensa assembler
 @cindex Xtensa assembler syntax
+@cindex FLIX syntax
 
 Block comments are delimited by @samp{/*} and @samp{*/}.  End of line
 comments may be introduced with either @samp{#} or @samp{//}.
@@ -113,11 +102,45 @@ Instructions consist of a leading opcode or macro name followed by
 whitespace and an optional comma-separated list of operands:
 
 @smallexample
-@var{opcode} [@var{operand},@dots{}]
+@var{opcode} [@var{operand}, @dots{}]
 @end smallexample
 
 Instructions must be separated by a newline or semicolon.
 
+FLIX instructions, which bundle multiple opcodes together in a single
+instruction, are specified by enclosing the bundled opcodes inside
+braces:
+
+@smallexample
+@{
+[@var{format}]
+@var{opcode0} [@var{operands}]
+@var{opcode1} [@var{operands}]
+@var{opcode2} [@var{operands}]
+@dots{}
+@}
+@end smallexample
+
+The opcodes in a FLIX instruction are listed in the same order as the
+corresponding instruction slots in the TIE format declaration.
+Directives and labels are not allowed inside the braces of a FLIX
+instruction.  A particular TIE format name can optionally be specified
+immediately after the opening brace, but this is usually unnecessary.
+The assembler will automatically search for a format that can encode the
+specified opcodes, so the format name need only be specified in rare
+cases where there is more than one applicable format and where it
+matters which of those formats is used.  A FLIX instruction can also be
+specified on a single line by separating the opcodes with semicolons:
+
+@smallexample
+@{ [@var{format};] @var{opcode0} [@var{operands}]; @var{opcode1} [@var{operands}]; @var{opcode2} [@var{operands}]; @dots{} @}
+@end smallexample
+
+The assembler can automatically bundle opcodes into FLIX instructions.
+It encodes the opcodes in order, one at a time,
+choosing the smallest format where each opcode can be encoded and
+filling unused instruction slots with no-ops.
+
 @menu
 * Xtensa Opcodes::              Opcode Naming Conventions.
 * Xtensa Registers::            Register Naming.
@@ -126,41 +149,30 @@ Instructions must be separated by a newline or semicolon.
 @node Xtensa Opcodes
 @subsection Opcode Names
 @cindex Xtensa opcode names
-@cindex opcode names, Xtenxa
+@cindex opcode names, Xtensa
 
 See the @cite{Xtensa Instruction Set Architecture (ISA) Reference
 Manual} for a complete list of opcodes and descriptions of their
 semantics.
 
-@cindex generic opcodes
-@cindex specific opcodes
 @cindex _ opcode prefix
-The Xtensa assembler distinguishes between @dfn{generic} and
-@dfn{specific} opcodes.  Specific opcodes correspond directly to Xtensa
-machine instructions.  Prefixing an opcode with an underscore character
-(@samp{_}) identifies it as a specific opcode.  Opcodes without a
-leading underscore are generic, which means the assembler is required to
-preserve their semantics but may not translate them directly to the
-specific opcodes with the same names.  Instead, the assembler may
-optimize a generic opcode and select a better instruction to use in its
-place (@pxref{Xtensa Optimizations, ,Xtensa Optimizations}), or the
-assembler may relax the instruction to handle operands that are out of
-range for the corresponding specific opcode (@pxref{Xtensa Relaxation,
-,Xtensa Relaxation}).
-
-Only use specific opcodes when it is essential to select
-the exact machine instructions produced by the assembler.
-Using specific opcodes unnecessarily only makes the code less
-efficient, by disabling assembler optimization, and less flexible, by
-disabling relaxation.
+If an opcode name is prefixed with an underscore character (@samp{_}),
+@command{@value{AS}} will not transform that instruction in any way.  The
+underscore prefix disables both optimization (@pxref{Xtensa
+Optimizations, ,Xtensa Optimizations}) and relaxation (@pxref{Xtensa
+Relaxation, ,Xtensa Relaxation}) for that particular instruction.  Only
+use the underscore prefix when it is essential to select the exact
+opcode produced by the assembler.  Using this feature unnecessarily
+makes the code less efficient by disabling assembler optimization and
+less flexible by disabling relaxation.
 
 Note that this special handling of underscore prefixes only applies to
 Xtensa opcodes, not to either built-in macros or user-defined macros.
-When an underscore prefix is used with a macro (e.g., @code{_NOP}), it
+When an underscore prefix is used with a macro (e.g., @code{_MOV}), it
 refers to a different macro.  The assembler generally provides built-in
 macros both with and without the underscore prefix, where the underscore
 versions behave as if the underscore carries through to the instructions
-in the macros.  For example, @code{_NOP} expands to @code{_OR a1,a1,a1}.
+in the macros.  For example, @code{_MOV} may expand to @code{_MOV.N}@.
 
 The underscore prefix only applies to individual instructions, not to
 series of instructions.  For example, if a series of instructions have
@@ -168,7 +180,7 @@ underscore prefixes, the assembler will not transform the individual
 instructions, but it may insert other instructions between them (e.g.,
 to align a @code{LOOP} instruction).  To prevent the assembler from
 modifying a series of instructions as a whole, use the
-@code{no-generics} directive.  @xref{Generics Directive, ,generics}.
+@code{no-transform} directive.  @xref{Transform Directive, ,transform}.
 
 @node Xtensa Registers
 @subsection Register Names
@@ -176,20 +188,20 @@ modifying a series of instructions as a whole, use the
 @cindex register names, Xtensa
 @cindex sp register
 
-An initial @samp{$} character is optional in all register names.
-General purpose registers are named @samp{a0}@dots{}@samp{a15}.  Additional
-registers may be added by processor configuration options.  In
-particular, the @sc{mac16} option adds a @sc{mr} register bank.  Its
-registers are named @samp{m0}@dots{}@samp{m3}.
-
-As a special feature, @samp{sp} is also supported as a synonym for
-@samp{a1}.
+The assembly syntax for a register file entry is the ``short'' name for
+a TIE register file followed by the index into that register file.  For
+example, the general-purpose @code{AR} register file has a short name of
+@code{a}, so these registers are named @code{a0}@dots{}@code{a15}.
+As a special feature, @code{sp} is also supported as a synonym for
+@code{a1}.  Additional registers may be added by processor configuration
+options and by designer-defined TIE extensions.  An initial @samp{$}
+character is optional in all register names.
 
 @node Xtensa Optimizations
 @section Xtensa Optimizations
 @cindex optimizations
 
-The optimizations currently supported by @code{@value{AS}} are
+The optimizations currently supported by @command{@value{AS}} are
 generation of density instructions where appropriate and automatic
 branch target alignment.
 
@@ -205,18 +217,18 @@ branch target alignment.
 The Xtensa instruction set has a code density option that provides
 16-bit versions of some of the most commonly used opcodes.  Use of these
 opcodes can significantly reduce code size.  When possible, the
-assembler automatically translates generic instructions from the core
+assembler automatically translates instructions from the core
 Xtensa instruction set into equivalent instructions from the Xtensa code
-density option.  This translation can be disabled by using specific
-opcodes (@pxref{Xtensa Opcodes, ,Opcode Names}), by using the
-@samp{--no-density} command-line option (@pxref{Xtensa Options, ,Command
-Line Options}), or by using the @code{no-density} directive
-(@pxref{Density Directive, ,density}).
+density option.  This translation can be disabled by using underscore
+prefixes (@pxref{Xtensa Opcodes, ,Opcode Names}), by using the
+@samp{--no-transform} command-line option (@pxref{Xtensa Options, ,Command
+Line Options}), or by using the @code{no-transform} directive
+(@pxref{Transform Directive, ,transform}).
 
 It is a good idea @emph{not} to use the density instructions directly.
 The assembler will automatically select dense instructions where
-possible.  If you later need to avoid using the code density option, you
-can disable it in the assembler without having to modify the code.
+possible.  If you later need to use an Xtensa processor without the code
+density option, the same assembly code will then work without modification.
 
 @node Xtensa Automatic Alignment
 @subsection Automatic Instruction Alignment
@@ -230,24 +242,42 @@ can disable it in the assembler without having to modify the code.
 The Xtensa assembler will automatically align certain instructions, both
 to optimize performance and to satisfy architectural requirements.
 
-When the @code{--target-@-align} command-line option is enabled
-(@pxref{Xtensa Options, ,Command Line Options}), the assembler attempts
-to widen density instructions preceding a branch target so that the
-target instruction does not cross a 4-byte boundary.  Similarly, the
-assembler also attempts to align each instruction following a call
-instruction.  If there are not enough preceding safe density
-instructions to align a target, no widening will be performed.  This
-alignment has the potential to reduce branch penalties at some expense
-in code size.  The assembler will not attempt to align labels with the
-prefixes @code{.Ln} and @code{.LM}, since these labels are used for
-debugging information and are not typically branch targets.
-
-The @code{LOOP} family of instructions must be aligned on either a 1 or
-2 mod 4 byte boundary.  The assembler knows about this restriction and
-inserts the minimal number of 2 or 3 byte no-op instructions
-to satisfy it.  When no-op instructions are added, any label immediately
-preceding the original loop will be moved in order to refer to the loop
-instruction, not the newly generated no-op instruction.
+As an optimization to improve performance, the assembler attempts to
+align branch targets so they do not cross instruction fetch boundaries.
+(Xtensa processors can be configured with either 32-bit or 64-bit
+instruction fetch widths.)  An
+instruction immediately following a call is treated as a branch target
+in this context, because it will be the target of a return from the
+call.  This alignment has the potential to reduce branch penalties at
+some expense in code size.  The assembler will not attempt to align
+labels with the prefixes @code{.Ln} and @code{.LM}, since these labels
+are used for debugging information and are not typically branch targets.
+This optimization is enabled by default.  You can disable it with the
+@samp{--no-target-@-align} command-line option (@pxref{Xtensa Options,
+,Command Line Options}).
+
+The target alignment optimization is done without adding instructions
+that could increase the execution time of the program.  If there are
+density instructions in the code preceding a target, the assembler can
+change the target alignment by widening some of those instructions to
+the equivalent 24-bit instructions.  Extra bytes of padding can be
+inserted immediately following unconditional jump and return
+instructions.
+This approach is usually successful in aligning many, but not all,
+branch targets.
+
+The @code{LOOP} family of instructions must be aligned such that the
+first instruction in the loop body does not cross an instruction fetch
+boundary (e.g., with a 32-bit fetch width, a @code{LOOP} instruction
+must be on either a 1 or 2 mod 4 byte boundary).  The assembler knows
+about this restriction and inserts the minimal number of 2 or 3 byte
+no-op instructions to satisfy it.  When no-op instructions are added,
+any label immediately preceding the original loop will be moved in order
+to refer to the loop instruction, not the newly generated no-op
+instruction.  To preserve binary compatibility across processors with
+different fetch widths, the assembler conservatively assumes a 32-bit
+fetch width when aligning @code{LOOP} instructions (except if the first
+instruction in the loop is a 64-bit instruction).
 
 Similarly, the @code{ENTRY} instruction must be aligned on a 0 mod 4
 byte boundary.  The assembler satisfies this requirement by inserting
@@ -260,7 +290,7 @@ location.
 @cindex relaxation
 
 When an instruction operand is outside the range allowed for that
-particular instruction field, @code{@value{AS}} can transform the code
+particular instruction field, @command{@value{AS}} can transform the code
 to use a functionally-equivalent instruction or sequence of
 instructions.  This process is known as @dfn{relaxation}.  This is
 typically done for branch instructions because the distance of the
@@ -300,6 +330,19 @@ M:
 (The @code{BNEZ.N} instruction would be used in this example only if the
 density option is available.  Otherwise, @code{BNEZ} would be used.)
 
+This relaxation works well because the unconditional jump instruction
+has a much larger offset range than the various conditional branches.
+However, an error will occur if a branch target is beyond the range of a
+jump instruction.  @command{@value{AS}} cannot relax unconditional jumps.
+Similarly, an error will occur if the original input contains an
+unconditional jump to a target that is out of range.
+
+Branch relaxation is enabled by default.  It can be disabled by using
+underscore prefixes (@pxref{Xtensa Opcodes, ,Opcode Names}), the
+@samp{--no-transform} command-line option (@pxref{Xtensa Options,
+,Command Line Options}), or the @code{no-transform} directive
+(@pxref{Transform Directive, ,transform}).
+
 @node Xtensa Call Relaxation
 @subsection Function Call Relaxation
 @cindex relaxation of call instructions
@@ -332,21 +375,27 @@ Because the addresses of targets of function calls are not generally
 known until link-time, the assembler must assume the worst and relax all
 the calls to functions in other source files, not just those that really
 will be out of range.  The linker can recognize calls that were
-unnecessarily relaxed, but it can only partially remove the overhead
-introduced by the assembler.
+unnecessarily relaxed, and it will remove the overhead introduced by the
+assembler for those cases where direct calls are sufficient.
 
-Call relaxation has a negative effect
-on both code size and performance, so this relaxation is disabled by 
-default.  If a program is too large and some of the calls are out of
-range, function call relaxation can be enabled using the
-@samp{--longcalls} command-line option or the @code{longcalls} directive
-(@pxref{Longcalls Directive, ,longcalls}).
+Call relaxation is disabled by default because it can have a negative
+effect on both code size and performance, although the linker can
+usually eliminate the unnecessary overhead.  If a program is too large
+and some of the calls are out of range, function call relaxation can be
+enabled using the @samp{--longcalls} command-line option or the
+@code{longcalls} directive (@pxref{Longcalls Directive, ,longcalls}).
 
 @node Xtensa Immediate Relaxation
 @subsection Other Immediate Field Relaxation
 @cindex immediate fields, relaxation
 @cindex relaxation of immediate fields
 
+The assembler normally performs the following other relaxations.  They
+can be disabled by using underscore prefixes (@pxref{Xtensa Opcodes,
+,Opcode Names}), the @samp{--no-transform} command-line option
+(@pxref{Xtensa Options, ,Command Line Options}), or the
+@code{no-transform} directive (@pxref{Transform Directive, ,transform}).
+
 @cindex @code{MOVI} instructions, relaxation
 @cindex relaxation of @code{MOVI} instructions
 The @code{MOVI} machine instruction can only materialize values in the
@@ -401,7 +450,7 @@ out-of-range offset causes an error.
 @cindex relaxation of @code{ADDI} instructions
 The Xtensa @code{ADDI} instruction only allows immediate operands in the
 range from -128 to 127.  There are a number of alternate instruction
-sequences for the generic @code{ADDI} operation.  First, if the
+sequences for the @code{ADDI} operation.  First, if the
 immediate is 0, the @code{ADDI} will be turned into a @code{MOV.N}
 instruction (or the equivalent @code{OR} instruction if the code density
 option is not available).  If the @code{ADDI} immediate is outside of
@@ -456,87 +505,49 @@ change the state of the directive without having to be aware of its
 outer state.  For example, consider:
 
 @smallexample
-    .begin no-density
+    .begin no-transform
 L:  add a0, a1, a2
-    .begin density
+    .begin transform
 M:  add a0, a1, a2
-    .end density
+    .end transform
 N:  add a0, a1, a2
-    .end no-density
+    .end no-transform
 @end smallexample
 
-The generic @code{ADD} opcodes at @code{L} and @code{N} in the outer
-@code{no-density} region both result in @code{ADD} machine instructions,
-but the assembler selects an @code{ADD.N} instruction for the generic
-@code{ADD} at @code{M} in the inner @code{density} region.
+The @code{ADD} opcodes at @code{L} and @code{N} in the outer
+@code{no-transform} region both result in @code{ADD} machine instructions,
+but the assembler selects an @code{ADD.N} instruction for the
+@code{ADD} at @code{M} in the inner @code{transform} region.
 
 The advantage of this style is that it works well inside macros which can
 preserve the context of their callers.
 
-@cindex precedence of directives
-@cindex directives, precedence
-When command-line options and assembler directives are used at the same
-time and conflict, the one that overrides a default behavior takes
-precedence over one that is the same as the default.  For example, if
-the code density option is available, the default is to select density
-instructions whenever possible.  So, if the above is assembled with the
-@samp{--no-density} flag, which overrides the default, all the generic
-@code{ADD} instructions result in @code{ADD} machine instructions.  If
-assembled with the @samp{--density} flag, which is already the default,
-the @code{no-density} directive takes precedence and only one of
-the generic @code{ADD} instructions is optimized to be a @code{ADD.N}
-machine instruction.  An underscore prefix identifying a specific opcode
-always takes precedence over directives and command-line flags.
-
 The following directives are available:
 @menu
-* Density Directive::          Disable Use of Density Instructions.
-* Relax Directive::            Disable Assembler Relaxation.
+* Schedule Directive::         Enable instruction scheduling.
 * Longcalls Directive::        Use Indirect Calls for Greater Range.
-* Generics Directive::         Disable All Assembler Transformations.
+* Transform Directive::        Disable All Assembler Transformations.
 * Literal Directive::          Intermix Literals with Instructions.
 * Literal Position Directive:: Specify Inline Literal Pool Locations.
 * Literal Prefix Directive::   Specify Literal Section Name Prefix.
-* Freeregs Directive::         List Registers Available for Assembler Use.
+* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals.
 * Frame Directive::            Describe a stack frame.
 @end menu
 
-@node Density Directive
-@subsection density
-@cindex @code{density} directive
-@cindex @code{no-density} directive
+@node Schedule Directive
+@subsection schedule
+@cindex @code{schedule} directive
+@cindex @code{no-schedule} directive
 
-The @code{density} and @code{no-density} directives enable or disable
-optimization of generic instructions into density instructions within
-the region.  @xref{Density Instructions, ,Using Density Instructions}.
+The @code{schedule} directive is recognized only for compatibility with
+Tensilica's assembler.
 
 @smallexample
-    .begin [no-]density
-    .end [no-]density
+    .begin [no-]schedule
+    .end [no-]schedule
 @end smallexample
 
-This optimization is enabled by default unless the Xtensa configuration
-does not support the code density option or the @samp{--no-density}
-command-line option was specified.
-
-@node Relax Directive
-@subsection relax
-@cindex @code{relax} directive
-@cindex @code{no-relax} directive
-
-The @code{relax} directive enables or disables relaxation
-within the region.  @xref{Xtensa Relaxation, ,Xtensa Relaxation}.
-Note: In the current implementation, these directives also control
-whether assembler optimizations are performed, making them equivalent to
-the @code{generics} and @code{no-generics} directives.
-
-@smallexample
-    .begin [no-]relax
-    .end [no-]relax
-@end smallexample
-
-Relaxation is enabled by default unless the @samp{--no-relax}
-command-line option was specified.
+This directive is ignored and has no effect on @command{@value{AS}}.
 
 @node Longcalls Directive
 @subsection longcalls
@@ -552,27 +563,28 @@ relaxation.  @xref{Xtensa Call Relaxation, ,Function Call Relaxation}.
 @end smallexample
 
 Call relaxation is disabled by default unless the @samp{--longcalls}
-command-line option is specified.
+command-line option is specified.  The @code{longcalls} directive
+overrides the default determined by the command-line options.
 
-@node Generics Directive
-@subsection generics
-@cindex @code{generics} directive
-@cindex @code{no-generics} directive
+@node Transform Directive
+@subsection transform
+@cindex @code{transform} directive
+@cindex @code{no-transform} directive
 
 This directive enables or disables all assembler transformation,
 including relaxation (@pxref{Xtensa Relaxation, ,Xtensa Relaxation}) and
 optimization (@pxref{Xtensa Optimizations, ,Xtensa Optimizations}).
 
 @smallexample
-    .begin [no-]generics
-    .end [no-]generics
+    .begin [no-]transform
+    .end [no-]transform
 @end smallexample
 
-Disabling generics is roughly equivalent to adding an underscore prefix
-to every opcode within the region, so that every opcode is treated as a
-specific opcode.  @xref{Xtensa Opcodes, ,Opcode Names}.  In the current
-implementation of @code{@value{AS}}, built-in macros are also disabled
-within a @code{no-generics} region.
+Transformations are enabled by default unless the @samp{--no-transform}
+option is used.  The @code{transform} directive overrides the default
+determined by the command-line options.  An underscore opcode prefix,
+disabling transformation of that opcode, always takes precedence over
+both directives and command-line flags.
 
 @node Literal Directive
 @subsection literal
@@ -603,17 +615,19 @@ can be used to load a pointer to the symbol @code{sym} into register
 @code{ENTRY} and @code{L32R} instructions; instead, the assembler puts
 the data in a literal pool.
 
-By default literal pools are placed in a separate section; however, when
+Literal pools for absolute mode @code{L32R} instructions
+(@pxref{Absolute Literals Directive}) are always placed in the
+@code{.lit4} section.  By default literal pools for PC-relative mode
+@code{L32R} instructions are placed in a separate section; however, when
 using the @samp{--text-@-section-@-literals} option (@pxref{Xtensa
 Options, ,Command Line Options}), the literal pools are placed in the
 current section.  These text section literal pools are created
 automatically before @code{ENTRY} instructions and manually after
 @samp{.literal_position} directives (@pxref{Literal Position Directive,
 ,literal_position}).  If there are no preceding @code{ENTRY}
-instructions or @code{.literal_position} directives, the assembler will
-print a warning and place the literal pool at the beginning of the
-current section.  In such cases, explicit @code{.literal_position}
-directives should be used to place the literal pools.
+instructions, explicit @code{.literal_position} directives
+must be used to place the text section literal pools; otherwise, 
+@command{@value{AS}} will report an error.
 
 @node Literal Position Directive
 @subsection literal_position
@@ -628,7 +642,8 @@ can be used to mark a potential location for a literal pool.
 @end smallexample
 
 The @code{.literal_position} directive is ignored when the
-@samp{--text-@-section-@-literals} option is not used.
+@samp{--text-@-section-@-literals} option is not used or when
+@code{L32R} instructions use the absolute addressing mode.
 
 The assembler will automatically place text section literal pools 
 before @code{ENTRY} instructions, so the @code{.literal_position}
@@ -642,7 +657,8 @@ place to put a literal pool.  Moreover, the code for the interrupt
 vector must be at a specific starting address, so the literal pool
 cannot come before the start of the code.  The literal pool for the
 vector must be explicitly positioned in the middle of the vector (before
-any uses of the literals, of course).  The @code{.literal_position}
+any uses of the literals, due to the negative offsets used by
+PC-relative @code{L32R} instructions).  The @code{.literal_position}
 directive can be used to do this.  In the following code, the literal
 for @samp{M} will automatically be aligned correctly and is placed after
 the unconditional jump.
@@ -663,6 +679,9 @@ continue:
 
 The @code{literal_prefix} directive allows you to specify different
 sections to hold literals from different portions of an assembly file.
+This directive only applies to literals referenced from PC-relative
+@code{L32R} instructions; it has no effect for absolute literals
+(@pxref{Absolute Literals Directive}).
 With this directive, a single assembly file can be used to generate code
 into multiple sections, including literals generated by the assembler.
 
@@ -679,31 +698,40 @@ the ``default'' for the file.  This default is usually @code{.literal}
 but can be changed with the @samp{--rename-section} command-line
 argument.
 
-@node Freeregs Directive
-@subsection freeregs
-@cindex @code{freeregs} directive
-
-This directive tells the assembler that the given registers are unused
-in the region.
-
-@smallexample
-    .begin freeregs @var{ri}[,@var{ri}@dots{}]
-    .end freeregs
-@end smallexample
-
-This allows the assembler to use these registers for relaxations or
-optimizations.  (They are actually only for relaxations at present, but
-the possibility of optimizations exists in the future.)
+@node Absolute Literals Directive
+@subsection absolute-literals
+@cindex @code{absolute-literals} directive
+@cindex @code{no-absolute-literals} directive
 
-Nested @code{freeregs} directives can be used to add additional registers
-to the list of those available to the assembler.  For example:
+The @code{absolute-@-literals} and @code{no-@-absolute-@-literals}
+directives control the absolute vs.@: PC-relative mode for @code{L32R}
+instructions.  These are relevant only for Xtensa configurations that
+include the absolute addressing option for @code{L32R} instructions.
 
 @smallexample
-    .begin freeregs a3, a4
-    .begin freeregs a5
+    .begin [no-]absolute-literals
+    .end [no-]absolute-literals
 @end smallexample
 
-has the effect of declaring @code{a3}, @code{a4}, and @code{a5} all free.
+These directives do not change the @code{L32R} mode---they only cause
+the assembler to emit the appropriate kind of relocation for @code{L32R}
+instructions and to place the literal values in the appropriate section.
+To change the @code{L32R} mode, the program must write the
+@code{LITBASE} special register.  It is the programmer's responsibility
+to keep track of the mode and indicate to the assembler which mode is
+used in each region of code.
+
+Literals referenced with absolute @code{L32R} instructions are always
+placed in the @code{.lit4} section.  PC-relative literals may be placed
+in the current text section or in a separate literal section, as
+described elsewhere (@pxref{Literal Directive}).
+
+If the Xtensa configuration includes the absolute @code{L32R} addressing
+option, the default is to assume absolute @code{L32R} addressing unless
+the @samp{--no-@-absolute-@-literals} command-line option is specified.
+Otherwise, the default is to assume PC-relative @code{L32R} addressing.
+The @code{absolute-@-literals} directive can then be used to override
+the default determined by the command-line options.
 
 @node Frame Directive
 @subsection frame
@@ -719,9 +747,9 @@ debugger to locate a function's stack frame.  The syntax is:
 where @var{reg} is the register used to hold the frame pointer (usually
 the same as the stack pointer) and @var{size} is the size in bytes of
 the stack frame.  The @code{.frame} directive is typically placed
-immediately after the @code{ENTRY} instruction for a function.
+near the @code{ENTRY} instruction for a function.
 
-In almost all circumstances, this information just duplicates the
+In many circumstances, this information just duplicates the
 information given in the function's @code{ENTRY} instruction; however,
 there are two cases where this is not true: