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| author | Nick Clifton <nickc@redhat.com> | 2000-09-14 01:47:38 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2000-09-14 01:47:38 +0000 |
| commit | 156c2f8bf75a86dfa719220f9f259196d9d2491b (patch) | |
| tree | 410e768f761f1c8884cc7529e6d449bde2d4dc26 /gas/doc | |
| parent | 9b14b192bba894ebaa57346c116d8feda54829de (diff) | |
| download | gdb-156c2f8bf75a86dfa719220f9f259196d9d2491b.zip gdb-156c2f8bf75a86dfa719220f9f259196d9d2491b.tar.gz gdb-156c2f8bf75a86dfa719220f9f259196d9d2491b.tar.bz2 | |
Add support for the MIPS32
Diffstat (limited to 'gas/doc')
| -rw-r--r-- | gas/doc/as.texinfo | 8 | ||||
| -rw-r--r-- | gas/doc/c-mips.texi | 3 |
2 files changed, 10 insertions, 1 deletions
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index f2f434c..110d23a 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -278,7 +278,7 @@ Here is a brief summary of how to invoke @code{@value{AS}}. For details, @end ifset @ifset MIPS [ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ] - [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -m4650 ] [ -no-m4650 ] + [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -m4650 ] [ -no-m4650 ] [ -mips32 ] [ -no-mips32 ] [ --trap ] [ --break ] [ --emulation=@var{name} ] @end ifset @@ -679,6 +679,12 @@ the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} instructions around accesses to the @samp{HI} and @samp{LO} registers. @samp{-no-m4650} turns off this option. +@item -mips32 +@itemx -no-mips32 +Generate code for the @sc{MIPS32} architecture. This tells the assembler to +accept ISA level 2 instructions and MIPS32 extensions including some @sc{r4000} +instructions. + @item -mcpu=@var{CPU} Generate code for a particular MIPS cpu. This has little effect on the assembler, but it is passed by @code{@value{GCC}}. diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi index 792b847..137dfe9 100644 --- a/gas/doc/c-mips.texi +++ b/gas/doc/c-mips.texi @@ -141,6 +141,9 @@ rm5721, rm7000, 8000, 10000 +4Kc +4Km +4Kp @end quotation |