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| author | H.J. Lu <hjl.tools@gmail.com> | 2020-01-27 04:38:10 -0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2020-01-27 04:38:29 -0800 |
| commit | bc31405ebb2c4297ae815ab59f59165014347528 (patch) | |
| tree | 4298be1f20f511497e961d2e672f38b0d2e75bf6 /gas/doc | |
| parent | e3696f67abfc46dcac6c9bbe47f8e25e34b17be5 (diff) | |
| download | gdb-bc31405ebb2c4297ae815ab59f59165014347528.zip gdb-bc31405ebb2c4297ae815ab59f59165014347528.tar.gz gdb-bc31405ebb2c4297ae815ab59f59165014347528.tar.bz2 | |
x86-64: Properly encode and decode movsxd
movsxd is a 64-bit only instruction. It supports both 16-bit and 32-bit
destination registers. Its AT&T mnemonic is movslq which only supports
64-bit destination register. There is also a discrepancy between AMD64
and Intel64 on movsxd with 16-bit destination register. AMD64 supports
32-bit source operand and Intel64 supports 16-bit source operand.
This patch updates movsxd encoding and decoding to alow 16-bit and 32-bit
destination registers. It also handles movsxd with 16-bit destination
register for AMD64 and Intel 64.
gas/
PR binutils/25445
* config/tc-i386.c (check_long_reg): Also convert to QWORD for
movsxd.
* doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA
differences. Document movslq and movsxd.
* testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests.
* testsuite/gas/i386/x86-64-movsxd-intel.d: New file.
* testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise.
* testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise.
* testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise.
* testsuite/gas/i386/x86-64-movsxd.d: Likewise.
* testsuite/gas/i386/x86-64-movsxd.s: Likewise.
opcodes/
PR binutils/25445
* i386-dis.c (MOVSXD_Fixup): New function.
(movsxd_mode): New enum.
(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
(intel_operand_size): Handle movsxd_mode.
(OP_E_register): Likewise.
(OP_G): Likewise.
* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
register on movsxd. Add movsxd with 16-bit destination register
for AMD64 and Intel64 ISAs.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'gas/doc')
| -rw-r--r-- | gas/doc/c-i386.texi | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 6d556a0..9fb681e 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -37,6 +37,7 @@ extending the Intel architecture to 64-bits. * i386-TBM:: AMD's Trailing Bit Manipulation Instructions * i386-16bit:: Writing 16-bit Code * i386-Arch:: Specifying an x86 CPU architecture +* i386-ISA:: AMD64 ISA vs. Intel64 ISA * i386-Bugs:: AT&T Syntax bugs * i386-Notes:: Notes @end menu @@ -856,6 +857,12 @@ Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp}, assembler with different mnemonics from those in Intel IA32 specification. @code{@value{GCC}} generates those instructions with AT&T mnemonic. +@itemize @bullet +@item @samp{movslq} with AT&T mnemonic only accepts 64-bit destination +register. @samp{movsxd} should be used to encode 16-bit or 32-bit +destination register with both AT&T and Intel mnemonics. +@end itemize + @node i386-Regs @section Register Naming @@ -1438,6 +1445,17 @@ For example .arch i8086,nojumps @end smallexample +@node i386-ISA +@section AMD64 ISA vs. Intel64 ISA + +There are some discrepancies between AMD64 and Intel64 ISAs. + +@itemize @bullet +@item For @samp{movsxd} with 16-bit destination register, AMD64 +supports 32-bit source operand and Intel64 supports 16-bit source +operand. +@end itemize + @node i386-Bugs @section AT&T Syntax bugs |