x86: Don't disable SSE4a when disabling SSE4

commit 7deea9aad8 changed nosse4 to include CpuSSE4a.  But AMD SSE4a is
a superset of SSE3 and Intel SSE4 is a superset of SSSE3.  Disable Intel
SSE4 shouldn't disable AMD SSE4a.  This patch restores nosse4.  It also
adds .sse4a and nosse4a.

gas/

	* config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a.  Restore
	nosse4.
	* doc/c-i386.texi: Document sse4a and nosse4a.

opcodes/

	* i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
	CPU_ANY_SSE4_FLAGS.

1 files changed, 3 insertions, 1 deletions

diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 235a395..91586cd 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -151,6 +151,7 @@ accept various extension mnemonics.  For example,
 @code{sse},
 @code{sse2},
 @code{sse3},
+@code{sse4a},
 @code{ssse3},
 @code{sse4.1},
 @code{sse4.2},
@@ -158,6 +159,7 @@ accept various extension mnemonics.  For example,
 @code{nosse},
 @code{nosse2},
 @code{nosse3},
+@code{nosse4a},
 @code{nossse3},
 @code{nosse4.1},
 @code{nosse4.2},
@@ -1428,7 +1430,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1}
 @item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
 @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
-@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
+@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @samp{.sse4a}
 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}