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author | Jan Beulich <jbeulich@suse.com> | 2019-07-01 08:33:56 +0200 |
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committer | Jan Beulich <jbeulich@suse.com> | 2019-07-01 08:33:56 +0200 |
commit | 79dec6b7baa243a4ada018a082491990adb6aec1 (patch) | |
tree | e77adf4f441561605525a616766898d5280192cb /gas/doc | |
parent | a80195f1224aced64392b452d55980b6bbd2a8b9 (diff) | |
download | gdb-79dec6b7baa243a4ada018a082491990adb6aec1.zip gdb-79dec6b7baa243a4ada018a082491990adb6aec1.tar.gz gdb-79dec6b7baa243a4ada018a082491990adb6aec1.tar.bz2 |
x86-64: optimize certain commutative VEX-encoded insns
When they're in the 0F opcode space, swapping their source operands may
allow switching from 3-byte to 2-byte VEX prefix encoding. Note that NaN
behavior precludes us doing so for many packed and scalar floating point
insns; such an optimization would need to be done by the compiler
instead in this case, when it knows that NaN-s have undefined behavior
anyway.
While for explicitly specified AVX/AVX2 insns the optimization (for now
at least) gets done only for -O2 and -Os, it is utilized by default in
SSE2AVX mode, as there we're re-writing the programmer's specified insns
anyway.
Rather than introducing a new attribute flag, the change re-uses one
which so far was meaningful only for EVEX-encoded insns.
Diffstat (limited to 'gas/doc')
-rw-r--r-- | gas/doc/c-i386.texi | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index ba20067..2ceb594 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -474,7 +474,10 @@ instructions with 128-bit/256-bit VEX packed integer logical. @samp{-O2} includes @samp{-O1} optimization plus encodes 256-bit/512-bit EVEX vector register clearing instructions with 128-bit -EVEX vector register clearing instructions. +EVEX vector register clearing instructions. In 64-bit mode VEX encoded +instructions with commutative source operands will also have their +source operands swapped if this allows using the 2-byte VEX prefix form +instead of the 3-byte one. @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with |