2001-06-28 Eric Christopher <echristo@redhat.com>

	    H.J. Lu  <hjl@gnu.org>

        * config/tc-mips.c (mips_arch): New. Use mips_arch instead
        of mips_cpu for the ISA selection.
        (md_longopts): Add OPTION_MARCH and OPTION_MTUNE.
        (md_parse_option): Handle OPTION_MARCH and OPTION_MTUNE.
	(mips_tune): New.  Use mips_tune for scheduling and optimization
	issues.
	(append_insn): Use mips_tune and mips_arch.
	(macro_build): Ditto.
	(mips_ip): Ditto.
	(md_begin): Handle mips_arch, mips_tune and mips_cpu.  For
	backwards compatability mips_cpu generates arch and tune.
	(md_show_usage): Document new behavior.

	* doc/c-mips.texi (MIPS Opts): Document -march and -mtune.
	Deprecate -mcpu.

	* NEWS: Update.

2001-06-28  Eric Christopher  <echristo@redhat.com>

	* gas/mips/usd.d: Change for march/mtune.
	* gas/mips/ulh-xgot.d: Ditto.
	* gas/mips/uld.d: Ditto.
	* gas/mips/trunc.d: Ditto.
	* gas/mips/rol.d: Ditto.
	* gas/mips/nodelay.d: Ditto.
	* gas/mips/mul.d: Ditto.
	* gas/mips/mul-ilocks.d: Ditto.
	* gas/mips/trap20.d: Ditto.
	* gas/mips/mips4.d: Ditto.
	* gas/mips/mips16.d: Ditto.
	* gas/mips/lif-xgot.d: Ditto.
	* gas/mips/lif-svr4pic.d: Ditto.
	* gas/mips/ld-xgot.d: Ditto.
	* gas/mips/ld-svr4pic.d: Ditto.
	* gas/mips/ld-ilocks-addr32.d: Ditto.
	* gas/mips/lb-xgot.d: Ditto.
	* gas/mips/jal-xgot.d: Ditto.
	* gas/mips/jal-svr4pic.d: Ditto.
	* gas/mips/delay.d: Ditto.
	* gas/mips/lb-xgot-ilocks.d: Ditto.
	* gas/mips/div.d: Ditto.
	* gas/mips/break20.d: Ditto.
	* gas/mips/delay.d: Ditto.
	* gas/mips/elf_e_flags3.d: Ditto.
	* gas/mips/elf_e_flags4.d: Ditto.
	* gas/mips/lineno.d: Ditto.
	* gas/mips/mips16.d: Ditto.
	* gas/mips/mips4.d: Ditto.
	* gas/mips/mips4010.d: Ditto.
	* gas/mips/mips4650.d: Ditto.

1 files changed, 14 insertions, 4 deletions

diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 64b7882..177e598 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -72,7 +72,7 @@ Generate code for a particular MIPS Instruction Set Architecture level.
 @samp{-mips64} correspond to generic @sc{MIPS V}, @sc{MIPS32}, and
 @sc{MIPS64} ISA processors, respectively.  You can also switch
 instruction sets during the assembly; see @ref{MIPS ISA, Directives to
-override the ISA level}. 
+override the ISA level}.
 
 @item -mgp32
 Assume that 32-bit general purpose registers are available.  This
@@ -121,7 +121,7 @@ For each option @samp{-m@var{nnnn}}, generate code for the MIPS
 @sc{r@var{nnnn}} chip.  This tells the assembler to accept instructions
 specific to that chip, and to schedule for that chip's hazards.
 
-@item -mcpu=@var{cpu}
+@item -march=@var{cpu}
 Generate code for a particular MIPS cpu.  It is exactly equivalent to
 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
 understood.  Valid @var{cpu} value are:
@@ -152,6 +152,16 @@ mips32-4k,
 sb1
 @end quotation
 
+@item -mtune=@var{cpu}
+Schedule and tune for a particular MIPS cpu.  Valid @var{cpu} values are
+identical to @samp{-march=@var{cpu}}.
+
+@item -mcpu=@var{cpu}
+Generate code and schedule for a particular MIPS cpu.  This is exactly
+equivalent to @samp{-march=@var{cpu}} and @samp{-mtune=@var{cpu}}.  Valid
+@var{cpu} values are identical to @samp{-march=@var{cpu}}.
+Use of this option is discouraged.
+
 
 @cindex @code{-nocpp} ignored (MIPS)
 @item -nocpp
@@ -258,13 +268,13 @@ mips0} restores the @sc{isa} level to its original level: either the
 level you selected with command line options, or the default for your
 configuration.  You can use this feature to permit specific @sc{r4000}
 instructions while assembling in 32 bit mode.  Use this directive with
-care! 
+care!
 
 The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
 in which it will assemble instructions for the MIPS 16 processor.  Use
 @samp{.set nomips16} to return to normal 32 bit mode.
 
-Traditional @sc{mips} assemblers do not support this directive.  
+Traditional @sc{mips} assemblers do not support this directive.
 
 @node MIPS autoextend
 @section Directives for extending MIPS 16 bit instructions