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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2002-09-30 12:04:54 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2002-09-30 12:04:54 +0000 |
| commit | 60b63b728f8bd4156ee67f70183fa01b425c2cba (patch) | |
| tree | 3cb3153bd6ad9d55ff9db92ff4d2c27dd7e7d565 /gas/doc/c-mips.texi | |
| parent | 9752cf1b67871d71ba4ccaf358e7550979bb4a3c (diff) | |
| download | gdb-60b63b728f8bd4156ee67f70183fa01b425c2cba.zip gdb-60b63b728f8bd4156ee67f70183fa01b425c2cba.tar.gz gdb-60b63b728f8bd4156ee67f70183fa01b425c2cba.tar.bz2 | |
[gas/]
* doc/c-mips.texi: Add entries for -march=vr4120,vr4130,vr4181,
vr5400 and vr5500. Add entry for -mfix-vr4122-bugs.
* config/tc-mips.c (CPU_HAS_DROR, CPU_HAS_ROR): New macros.
(hilo_interlocks): True for CPU_VR5500.
(gpr_interlocks, cop_interlocks): True for CPU_VR5400 and CPU_VR5500.
(mips_fix_vr4122_bugs): New.
(append_insn): Work around 4122 errors if mips_fix_vr4122_bugs.
(mips_emit_delays): Likewise.
(macro2) [M_DROLI]: Use dror or dror32 if CPU_HAS_DROR.
[M_ROLI]: Likewise ror if CPU_HAS_ROR.
(validate_mips_insn, mips_ip): Handle '[', ']', 'e' and '%'.
(OPTION_FIX_VR4122, OPTION_NO_FIX_VR4122): New options.
(md_longopts): Add -mfix-vr4122-bugs and -no-mfix-vr4122-bugs.
(OPTION_ELF_BASE): Bump.
(md_parse_option): Handle the new options.
(mips_cpu_info_table): Add entries for vr4120, vr4130, vr4181,
vr5400 and vr5500.
[gas/testsuite/]
* gas/mips/mips4100.[sd]: Move dmadd16 and madd16 checks to...
* gas/mips/vr4111.[sd]: ...this new test.
* gas/mips/vr4120.[sd],
* gas/mips/vr4122.[sd],
* gas/mips/vr5400.[sd],
* gas/mips/vr5500.[sd]: New tests.
* mips.exp: Run them.
Diffstat (limited to 'gas/doc/c-mips.texi')
| -rw-r--r-- | gas/doc/c-mips.texi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi index b19c09b..6b82fd0 100644 --- a/gas/doc/c-mips.texi +++ b/gas/doc/c-mips.texi @@ -116,6 +116,12 @@ This tells the assembler to accept MDMX instructions. Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions. +@item -mfix-vr4122-bugs +@itemx -no-mfix-vr4122-bugs +Insert @samp{nop} instructions to avoid errors in certain versions of +the vr4122 core. This option is intended to be used on GCC-generated +code: it is not designed to catch errors in hand-written assembler code. + @item -m4010 @itemx -no-m4010 Generate code for the LSI @sc{r4010} chip. This tells the assembler to @@ -152,6 +158,9 @@ understood. Valid @var{cpu} value are: 4010, 4100, 4111, +vr4120, +vr4130, +vr4181, 4300, 4400, 4600, @@ -162,6 +171,8 @@ rm5230, rm5231, rm5261, rm5721, +vr5400, +vr5500, 6000, rm7000, 8000, |