Add support for 64-bit ARM architecture: AArch64

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+@c Copyright 2009, 2010, 2011, 2012  Free Software Foundation, Inc.
+@c Contributed by ARM Ltd.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@c man end
+
+@ifset GENERIC
+@page
+@node AArch64-Dependent
+@chapter AArch64 Dependent Features
+@end ifset
+
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter AArch64 Dependent Features
+@end ifclear
+
+@cindex AArch64 support
+@cindex Thumb support
+@menu
+* AArch64 Options::              Options
+* AArch64 Syntax::               Syntax
+* AArch64 Floating Point::       Floating Point
+* AArch64 Directives::           AArch64 Machine Directives
+* AArch64 Opcodes::              Opcodes
+* AArch64 Mapping Symbols::      Mapping Symbols
+@end menu
+
+@node AArch64 Options
+@section Options
+@cindex AArch64 options (none)
+@cindex options for AArch64 (none)
+
+@c man begin OPTIONS
+@table @gcctabopt
+
+@cindex @code{-EB} command line option, AArch64
+@item -EB
+This option specifies that the output generated by the assembler should
+be marked as being encoded for a big-endian processor.
+
+@cindex @code{-EL} command line option, AArch64
+@item -EL
+This option specifies that the output generated by the assembler should
+be marked as being encoded for a little-endian processor.
+
+@end table
+@c man end
+
+@node AArch64 Syntax
+@section Syntax
+@menu
+* AArch64-Chars::                Special Characters
+* AArch64-Regs::                 Register Names
+* AArch64-Relocations::	     Relocations
+@end menu
+
+@node AArch64-Chars
+@subsection Special Characters
+
+@cindex line comment character, AArch64
+@cindex AArch64 line comment character
+The presence of a @samp{//} on a line indicates the start of a comment
+that extends to the end of the current line.  If a @samp{#} appears as
+the first character of a line, the whole line is treated as a comment.
+
+@cindex line separator, AArch64
+@cindex statement separator, AArch64
+@cindex AArch64 line separator
+The @samp{;} character can be used instead of a newline to separate
+statements.
+
+@cindex immediate character, AArch64
+@cindex AArch64 immediate character
+The @samp{#} can be optionally used to indicate immediate operands.
+
+@node AArch64-Regs
+@subsection Register Names
+
+@cindex AArch64 register names
+@cindex register names, AArch64
+Please refer to the section @samp{4.4 Register Names} of
+@samp{ARMv8 Instruction Set Overview}, which is available at
+@uref{http://infocenter.arm.com}.
+
+@node AArch64-Relocations
+@subsection Relocations
+
+@cindex relocations, AArch64
+@cindex AArch64 relocations
+@cindex MOVN, MOVZ and MOVK group relocations, AArch64
+Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
+by prefixing the label with @samp{#:abs_g2:} etc.
+For example to load the 48-bit absolute address of @var{foo} into x0:
+
+@smallexample
+        movz x0, #:abs_g2:foo		// bits 32-47, overflow check
+        movk x0, #:abs_g1_nc:foo	// bits 16-31, no overflow check
+        movk x0, #:abs_g0_nc:foo	// bits  0-15, no overflow check
+@end smallexample
+
+@cindex ADRP, ADD, LDR/STR group relocations, AArch64
+Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
+instructions can be generated by prefixing the label with
+@samp{#:pg_hi21:} and @samp{#:lo12:} respectively.
+
+For example to use 33-bit (+/-4GB) pc-relative addressing to 
+load the address of @var{foo} into x0:
+
+@smallexample
+        adrp x0, #:pg_hi21:foo
+        add  x0, x0, #:lo12:foo
+@end smallexample
+
+Or to load the value of @var{foo} into x0:
+
+@smallexample
+        adrp x0, #:pg_hi21:foo
+        ldr  x0, [x0, #:lo12:foo]
+@end smallexample
+
+Note that @samp{#:pg_hi21:} is optional.
+
+@smallexample
+        adrp x0, foo
+@end smallexample
+
+is equivalent to
+
+@smallexample
+        adrp x0, #:pg_hi21:foo
+@end smallexample
+
+@node AArch64 Floating Point
+@section Floating Point
+
+@cindex floating point, AArch64 (@sc{ieee})
+@cindex AArch64 floating point (@sc{ieee})
+The AArch64 architecture uses @sc{ieee} floating-point numbers.
+
+@node AArch64 Directives
+@section AArch64 Machine Directives
+
+@cindex machine directives, AArch64
+@cindex AArch64 machine directives
+@table @code
+
+@c AAAAAAAAAAAAAAAAAAAAAAAAA
+@c BBBBBBBBBBBBBBBBBBBBBBBBBB
+
+@cindex @code{.bss} directive, AArch64
+@item .bss
+This directive switches to the @code{.bss} section.
+
+@c CCCCCCCCCCCCCCCCCCCCCCCCCC
+@c DDDDDDDDDDDDDDDDDDDDDDDDDD
+@c EEEEEEEEEEEEEEEEEEEEEEEEEE
+@c FFFFFFFFFFFFFFFFFFFFFFFFFF
+@c GGGGGGGGGGGGGGGGGGGGGGGGGG
+@c HHHHHHHHHHHHHHHHHHHHHHHHHH
+@c IIIIIIIIIIIIIIIIIIIIIIIIII
+@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
+@c KKKKKKKKKKKKKKKKKKKKKKKKKK
+@c LLLLLLLLLLLLLLLLLLLLLLLLLL
+
+@cindex @code{.ltorg} directive, AArch64
+@item .ltorg
+This directive causes the current contents of the literal pool to be
+dumped into the current section (which is assumed to be the .text
+section) at the current location (aligned to a word boundary).
+@code{GAS} maintains a separate literal pool for each section and each
+sub-section.  The @code{.ltorg} directive will only affect the literal
+pool of the current section and sub-section.  At the end of assembly
+all remaining, un-empty literal pools will automatically be dumped.
+
+Note - older versions of @code{GAS} would dump the current literal
+pool any time a section change occurred.  This is no longer done, since
+it prevents accurate control of the placement of literal pools.
+
+@c MMMMMMMMMMMMMMMMMMMMMMMMMM
+
+@c NNNNNNNNNNNNNNNNNNNNNNNNNN
+@c OOOOOOOOOOOOOOOOOOOOOOOOOO
+
+@c PPPPPPPPPPPPPPPPPPPPPPPPPP
+
+@cindex @code{.pool} directive, AArch64
+@item .pool
+This is a synonym for .ltorg.
+
+@c QQQQQQQQQQQQQQQQQQQQQQQQQQ
+@c RRRRRRRRRRRRRRRRRRRRRRRRRR
+
+@cindex @code{.req} directive, AArch64
+@item @var{name} .req @var{register name}
+This creates an alias for @var{register name} called @var{name}.  For
+example:
+
+@smallexample
+        foo .req w0
+@end smallexample
+
+@c SSSSSSSSSSSSSSSSSSSSSSSSSS
+
+@c TTTTTTTTTTTTTTTTTTTTTTTTTT
+
+@c UUUUUUUUUUUUUUUUUUUUUUUUUU
+
+@cindex @code{.unreq} directive, AArch64
+@item .unreq @var{alias-name}
+This undefines a register alias which was previously defined using the
+@code{req} directive.  For example:
+
+@smallexample
+        foo .req w0
+        .unreq foo
+@end smallexample
+
+An error occurs if the name is undefined.  Note - this pseudo op can
+be used to delete builtin in register name aliases (eg 'w0').  This
+should only be done if it is really necessary.
+
+@c VVVVVVVVVVVVVVVVVVVVVVVVVV
+
+@c WWWWWWWWWWWWWWWWWWWWWWWWWW
+@c XXXXXXXXXXXXXXXXXXXXXXXXXX
+@c YYYYYYYYYYYYYYYYYYYYYYYYYY
+@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
+
+@end table
+
+@node AArch64 Opcodes
+@section Opcodes
+
+@cindex AArch64 opcodes
+@cindex opcodes for AArch64
+@code{@value{AS}} implements all the standard AArch64 opcodes.  It also
+implements several pseudo opcodes, including several synthetic load
+instructions. 
+
+@table @code
+
+@cindex @code{LDR reg,=<expr>} pseudo op, AArch64
+@item LDR =
+@smallexample
+  ldr <register> , =<expression>
+@end smallexample
+
+The constant expression will be placed into the nearest literal pool (if it not
+already there) and a PC-relative LDR instruction will be generated.
+
+@end table
+
+For more information on the AArch64 instruction set and assembly language
+notation, see @samp{ARMv8 Instruction Set Overview} available at
+@uref{http://infocenter.arm.com}.
+
+
+@node AArch64 Mapping Symbols
+@section Mapping Symbols
+
+The AArch64 ELF specification requires that special symbols be inserted
+into object files to mark certain features:
+
+@table @code
+
+@cindex @code{$x}
+@item $x
+At the start of a region of code containing AArch64 instructions.
+
+@cindex @code{$d}
+@item $d
+At the start of a region of data.
+
+@end table