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| author | Marcus Comstedt <marcus@mc.pp.se> | 2021-01-05 22:50:32 +0100 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2021-01-06 17:57:52 +0800 |
| commit | fbc09e7af715f19f6e5c700a9df6d13cdd05e1e5 (patch) | |
| tree | b7cfb144e27508c018d5ea332e56d36548216e9b /gas/configure.tgt | |
| parent | 865288236d881acecdcf0aaa636fd28fd811d862 (diff) | |
| download | gdb-fbc09e7af715f19f6e5c700a9df6d13cdd05e1e5.zip gdb-fbc09e7af715f19f6e5c700a9df6d13cdd05e1e5.tar.gz gdb-fbc09e7af715f19f6e5c700a9df6d13cdd05e1e5.tar.bz2 | |
RISC-V: Implement support for big endian targets.
RISC-V instruction/code is always little endian, but data might be
big-endian. Therefore, we can not use the original bfd_get/bfd_put
to get/put the code for big endian targets. Add new riscv_get_insn
and riscv_put_insn to always get/put code as little endian can resolve
the problem. Just remember to update them once we have supported
the 48-bit/128-bit instructions in the future patches.
bfd/
* config.bfd: Added targets riscv64be*-*-*, riscv32be*-*-* and
riscvbe*-*-*. Also added riscv_elf[32|64]_be_vec.
* configure.ac: Handle riscv_elf[32|64]_be_vec.
* configure: Regenerate.
* elfnn-riscv.c: Include <limits.h> and define CHAR_BIT for
riscv_is_insn_reloc.
(riscv_get_insn): RISC-V instructions are always little endian, but
bfd_get may be used for big-endian, so add new riscv_get_insn to handle
the insturctions.
(riscv_put_insn): Likewsie.
(riscv_is_insn_reloc): Check if we are relocaing an instruction.
(perform_relocation): Call riscv_is_insn_reloc to decide if we should
use riscv_[get|put]_insn or bfd_[get|put].
(riscv_zero_pcrel_hi_reloc): Use riscv_[get|put]_insn, bfd_[get|put]l32
or bfd_[get|put]l16 for code.
(riscv_elf_relocate_section): Likewise.
(riscv_elf_finish_dynamic_symbol): Likewise.
(riscv_elf_finish_dynamic_sections): Likewise.
(_bfd_riscv_relax_call): Likewise.
(_bfd_riscv_relax_lui): Likewise.
(_bfd_riscv_relax_align): Likewise.
(_bfd_riscv_relax_pc): Likewise.
(riscv_elf_object_p): Handled for big endian.
(TARGET_BIG_SYM, TARGET_BIG_NAME): Defined.
* targets.c: Add riscv_elf[32|64]_be_vec.
(_bfd_target_vector): Likewise.
gas/
* config/tc-riscv.c (riscv_target_format): Add elf64-bigriscv and
elf32-bigriscv.
(install_insn): Always write instructions as little endian.
(riscv_make_nops): Likewise.
(md_convert_frag_branch): Likewise.
(md_number_to_chars): Write data in target endianness.
(options, md_longopts): Add -mbig-endian and -mlittle-endian options.
(md_parse_option): Handle the endian options.
* config/tc-riscv.h: Only define TARGET_BYTES_BIG_ENDIAN if not
already defined.
* configure.tgt: Added riscv64be*, riscv32be*, riscvbe*.
ld/
* configure.tgt: Added riscvbe-*-*, riscv32be*-*-*, riscv64be*-*-*,
riscv32be*-*-linux*, and riscv64be*-*-linux*.
* Makefile.am: Added eelf32briscv.c, eelf32briscv_ilp32f.c and
eelf32briscv_ilp32.c.
* Makefile.in: Regenerate.
* emulparams/elf32briscv.sh: Added.
* emulparams/elf32briscv_ilp32.sh: Likewise.
* emulparams/elf32briscv_ilp32f.sh: Likewise.
* emulparams/elf64briscv.sh: Likewise.
* emulparams/elf64briscv_lp64.sh: Likewise.
* emulparams/elf64briscv_lp64f.sh: Likewise.
Diffstat (limited to 'gas/configure.tgt')
| -rw-r--r-- | gas/configure.tgt | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/gas/configure.tgt b/gas/configure.tgt index b17336b..6f46e0a 100644 --- a/gas/configure.tgt +++ b/gas/configure.tgt @@ -89,7 +89,9 @@ case ${cpu} in pj*) cpu_type=pj endian=big ;; powerpc*le*) cpu_type=ppc endian=little ;; powerpc*) cpu_type=ppc endian=big ;; + riscv64be*) cpu_type=riscv endian=big arch=riscv64 ;; riscv64*) cpu_type=riscv endian=little arch=riscv64 ;; + riscv32be*|riscvbe*) cpu_type=riscv endian=big arch=riscv32 ;; riscv32* | riscv*) cpu_type=riscv endian=little arch=riscv32 ;; rs6000*) cpu_type=ppc ;; rl78*) cpu_type=rl78 ;; @@ -357,7 +359,7 @@ case ${generic_target} in pru-*-*) fmt=elf ;; - riscv*-*-*) fmt=elf endian=little ;; + riscv*-*-*) fmt=elf ;; rx-*-linux*) fmt=elf em=linux ;; |