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authorAlan Modra <amodra@gmail.com>2002-07-08 10:03:11 +0000
committerAlan Modra <amodra@gmail.com>2002-07-08 10:03:11 +0000
commitcd61ebfe13189cd946e02dd5b6a8a53ca2a6c018 (patch)
tree6ff93da570047971b3c01cf14cca417623707982 /gas/config
parentaecc8f8acd0b3be16ffe73ddec39d5eb9816c7fa (diff)
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gas/ChangeLog
* config/tc-i386.c (process_suffix): Remove intel mode movsx and movzx fudges. (md_assemble): Instead, zap the suffix here. include/opcode/ChangeLog * i386.h: Remove IgnoreSize from movsx and movzx.
Diffstat (limited to 'gas/config')
-rw-r--r--gas/config/tc-i386.c30
1 files changed, 13 insertions, 17 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 653245f..5cf8251 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1326,11 +1326,19 @@ md_assemble (line)
if (!match_template ())
return;
- /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
- if (SYSV386_COMPAT
- && intel_syntax
- && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
- i.tm.base_opcode ^= FloatR;
+ if (intel_syntax)
+ {
+ /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
+ if (SYSV386_COMPAT
+ && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
+ i.tm.base_opcode ^= FloatR;
+
+ /* Zap movzx and movsx suffix. The suffix may have been set from
+ "word ptr" or "byte ptr" on the source operand, but we'll use
+ the suffix later to choose the destination register. */
+ if ((i.tm.base_opcode & ~9) == 0x0fb6)
+ i.suffix = 0;
+ }
if (i.tm.opcode_modifier & FWait)
if (!add_prefix (FWAIT_OPCODE))
@@ -2218,18 +2226,6 @@ process_suffix ()
return 0;
}
- /* For movzx and movsx, need to check the register type. */
- if (intel_syntax
- && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)
- && i.suffix == BYTE_MNEM_SUFFIX)
- {
- unsigned int prefix = DATA_PREFIX_OPCODE;
-
- if ((i.op[1].regs->reg_type & Reg16) != 0)
- if (!add_prefix (prefix))
- return 0;
- }
-
if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
{
/* It's not a byte, select word/dword operation. */