RISC-V: Update the riscv_opts.[rvc|rve] in the riscv_set_arch.

We also need to update the riscv_opts.[rvc|rve] for elf attributes.
Otherwise, the following case will fail,

$ cat cadd.s
.attribute arch, "rv64gc"
c.add   a0, a1
$ riscv64-unknown-elf-as cadd.s -o cadd.o
cadd.s: Assembler messages:
cadd.s:2: Error: illegal operands `c.add a0,a1

After applying this patch,

$ riscv64-unknown-elf-as cadd.s -o cadd.o
$ riscv64-unknown-elf-objdump -d cadd.o

cadd.o:     file format elf64-littleriscv

Disassembly of section .text:

0000000000000000 <.text>:
   0:   952e                    add     a0,a0,a1
        ...

gas/
    * config/tc-riscv.c (riscv_set_arch): Call riscv_set_rvc
    and riscv_set_rve both for -march and elf attributes.
    (riscv_after_parse_args): Likewise.

1 files changed, 8 insertions, 10 deletions

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 42e5752..70cbc81 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -417,6 +417,14 @@ riscv_set_arch (const char *s)
 
   riscv_release_subset_list (&riscv_subsets);
   riscv_parse_subset (&rps, s);
+
+  /* To support .option rvc and rve.  */
+  riscv_set_rvc (false);
+  if (riscv_subset_supports ("c"))
+    riscv_set_rvc (true);
+  riscv_set_rve (false);
+  if (riscv_subset_supports ("e"))
+    riscv_set_rve (true);
 }
 
 /* Indicate -mabi option is explictly set.  */
@@ -2945,16 +2953,6 @@ riscv_after_parse_args (void)
 
   riscv_set_arch (default_arch_with_ext);
 
-  /* Add the RVC extension, regardless of -march, to support .option rvc.  */
-  riscv_set_rvc (false);
-  if (riscv_subset_supports ("c"))
-    riscv_set_rvc (true);
-
-  /* Enable RVE if specified by the -march option.  */
-  riscv_set_rve (false);
-  if (riscv_subset_supports ("e"))
-    riscv_set_rve (true);
-
   /* If the CIE to be produced has not been overridden on the command line,
      then produce version 3 by default.  This allows us to use the full
      range of registers in a .cfi_return_column directive.  */