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| author | Chris Demetriou <cgd@google.com> | 2004-01-25 06:01:03 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2004-01-25 06:01:03 +0000 |
| commit | c8978940ea39a9b231a3d3295fbbf229992c9223 (patch) | |
| tree | bca1dde289a3012a51b3612891dea316f430a8e8 /gas/config | |
| parent | 424688adb823c724b796e928c5e25d5b7491b27c (diff) | |
| download | gdb-c8978940ea39a9b231a3d3295fbbf229992c9223.zip gdb-c8978940ea39a9b231a3d3295fbbf229992c9223.tar.gz gdb-c8978940ea39a9b231a3d3295fbbf229992c9223.tar.bz2 | |
2004-01-24 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (hilo_interlocks): Change definition
so that MIPS32, MIPS64 and later ISAs are included, along with
the already-included machines. Update comments.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-mips.c | 33 |
1 files changed, 24 insertions, 9 deletions
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 201eb61..42efce3 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -325,15 +325,30 @@ static int mips_32bitmode = 0; /* True if CPU has a ror instruction. */ #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) -/* Whether the processor uses hardware interlocks to protect - reads from the HI and LO registers, and thus does not - require nops to be inserted. */ - -#define hilo_interlocks (mips_opts.arch == CPU_R4010 \ - || mips_opts.arch == CPU_VR5500 \ - || mips_opts.arch == CPU_RM7000 \ - || mips_opts.arch == CPU_SB1 \ - ) +/* True if mflo and mfhi can be immediately followed by instructions + which write to the HI and LO registers. + + According to MIPS specifications, MIPS ISAs I, II, and III need + (at least) two instructions between the reads of HI/LO and + instructions which write them, and later ISAs do not. Contradicting + the MIPS specifications, some MIPS IV processor user manuals (e.g. + the UM for the NEC Vr5000) document needing the instructions between + HI/LO reads and writes, as well. Therefore, we declare only MIPS32, + MIPS64 and later ISAs to have the interlocks, plus any specific + earlier-ISA CPUs for which CPU documentation declares that the + instructions are really interlocked. */ +#define hilo_interlocks \ + (mips_opts.isa == ISA_MIPS32 \ + || mips_opts.isa == ISA_MIPS32R2 \ + || mips_opts.isa == ISA_MIPS64 \ + || mips_opts.isa == ISA_MIPS64R2 \ + || mips_opts.arch == CPU_R4010 \ + || mips_opts.arch == CPU_R10000 \ + || mips_opts.arch == CPU_R12000 \ + || mips_opts.arch == CPU_RM7000 \ + || mips_opts.arch == CPU_SB1 \ + || mips_opts.arch == CPU_VR5500 \ + ) /* Whether the processor uses hardware interlocks to protect reads from the GPRs after they are loaded from memory, and thus does not |