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authorMatthew Gretton-Dann <matthew.gretton-dann@arm.com>2012-08-24 08:01:18 +0000
committerMatthew Gretton-Dann <matthew.gretton-dann@arm.com>2012-08-24 08:01:18 +0000
commit53c4b28b4f873fd41d158eb9f23b2d07e2780b98 (patch)
treeee108b7763d5cb1be914bf911564fc8416b4ab34 /gas/config
parente797f7e0b2bedc9328d4a9a0ebc63ca7a2dbbebc (diff)
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* gas/config/tc-arm.c (T16_32_TAB): Add _sevl.
(insns): Add SEVL. * gas/testsuite/gas/arm/armv8-a.s: New testcase. * gas/testsuite/gas/arm/armv8-a.d: Likewise. * opcodes/arm-dis.c (arm_opcodes): Add SEVL. (thumb_opcodes): Likewise. (thumb32_opcodes): Likewise.
Diffstat (limited to 'gas/config')
-rw-r--r--gas/config/tc-arm.c13
1 files changed, 12 insertions, 1 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index d3838ab..cfcdecb 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -9549,7 +9549,8 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_yield, bf10, f3af8001), \
X(_wfe, bf20, f3af8002), \
X(_wfi, bf30, f3af8003), \
- X(_sev, bf40, f3af8004),
+ X(_sev, bf40, f3af8004), \
+ X(_sevl, bf50, f3af8005)
/* To catch errors in encoding functions, the codes are all offset by
0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
@@ -17966,8 +17967,18 @@ static const struct asm_opcode insns[] =
TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
+ /* AArchv8 instructions. */
+#undef ARM_VARIANT
+#define ARM_VARIANT & arm_ext_v8
+#undef THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_v8
+
+ tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
+
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
+#undef THUMB_VARIANT
+#define THUMB_VARIANT NULL
cCE("wfs", e200110, 1, (RR), rd),
cCE("rfs", e300110, 1, (RR), rd),