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| author | Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> | 2014-10-31 13:48:04 -0700 |
|---|---|---|
| committer | Andrew Pinski <apinski@cavium.com> | 2014-10-31 13:50:10 -0700 |
| commit | 2c62985659da21a3fe16062d211a7158f79ad2e9 (patch) | |
| tree | a0bf9d9f8326d5a0729e286c907599c2cff4d75a /gas/config | |
| parent | 222016651396c7baea9ff3f96003bd53bbc11ab0 (diff) | |
| download | gdb-2c62985659da21a3fe16062d211a7158f79ad2e9.zip gdb-2c62985659da21a3fe16062d211a7158f79ad2e9.tar.gz gdb-2c62985659da21a3fe16062d211a7158f79ad2e9.tar.bz2 | |
MIPS: Add Octeon 3 support
binutils:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* readelf.c (print_mips_isa_ext): Print the value of Octeon3.
gas:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* config/tc-mips.c (CPU_IS_OCTEON): Handle CPU_OCTEON3.
(mips_cpu_info_table): Octeon3 enables virt ase.
* doc/c-mips.texi: Document octeon3 as an acceptable value for
-march=.
gas/testsuite:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* gas/mips/mips.exp: Add support for Octeon3 architecture.
Also add in support for running Octeon3 tests.
* gas/mips/octeon3.d: New test.
* gas/mips/octeon3.s: New test source.
opcodes:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* mips-dis.c (mips_arch_choices): Add octeon3.
* mips-opc.c (IOCT): Include INSN_OCTEON3.
(IOCT2): Likewise.
(IOCT3): New define.
(IVIRT): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
IVIRT instructions.
Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
operand for IOCT3.
bfd:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* archures.c: Add octeon3 for mips target.
* bfd-in2.h: Regenerate.
* bfd/cpu-mips.c: Define I_mipsocteon3.
nfo_struct): Add octeon3 support.
* bfd/elfxx-mips.c: (_bfd_elf_mips_mach): Add support for
octeon3.
(mips_set_isa_flags): Add support for octeon3.
(bfd_mips_isa_ext): Add bfd_mach_mips_octeon3.
(mips_mach_extensions): Make bfd_mach_mips_octeon3 an
extension of bfd_mach_mips_octeon2.
(print_mips_isa_ext): Print the value of Octeon3.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-mips.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 54442f4..355a566 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -510,7 +510,8 @@ static int mips_32bitmode = 0; #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) /* True if CPU is in the Octeon family */ -#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2) +#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ + || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) /* True if CPU has seq/sne and seqi/snei instructions. */ #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) @@ -18663,6 +18664,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, + { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, /* RMI Xlr */ { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |