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| author | Mark Mitchell <mark@codesourcery.com> | 2009-03-02 00:29:23 +0000 |
|---|---|---|
| committer | Mark Mitchell <mark@codesourcery.com> | 2009-03-02 00:29:23 +0000 |
| commit | 04e2c417f9d55d3a9abf23a78a36a863886b8059 (patch) | |
| tree | abb88394766c7c17bd22e8e21bcaf1fee71db0ef /gas/config | |
| parent | c493b4aa97b99c95f55342cbf7e89c0e276be99c (diff) | |
| download | gdb-04e2c417f9d55d3a9abf23a78a36a863886b8059.zip gdb-04e2c417f9d55d3a9abf23a78a36a863886b8059.tar.gz gdb-04e2c417f9d55d3a9abf23a78a36a863886b8059.tar.bz2 | |
* config/tc-arm.c (md_assemble): Allow barrier instructions on
ARMv6-M cores.
* gas/arm/archv6m.s: Add dmb, dsb, and isb.
* gas/arm/archv6m.d: Likewise.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-arm.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index a1e5d12..bb783bd 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -14747,7 +14747,8 @@ md_assemble (char *str) /* Implicit require narrow instructions on Thumb-1. This avoids relaxation accidentally introducing Thumb-2 instructions. */ if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23 - && !ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)) + && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr) + || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier))) inst.size_req = 2; } @@ -14805,7 +14806,8 @@ md_assemble (char *str) This is overly pessimistic for relaxable instructions. */ if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) || inst.relax) - && !ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)) + && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr) + || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier))) ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_v6t2); } |