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| author | Jan Beulich <jbeulich@suse.com> | 2020-03-06 08:52:12 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2020-03-06 08:52:12 +0100 |
| commit | 643bb87079dd96aed99ff1572375a88179afcd15 (patch) | |
| tree | b374822f5d5bf82f49101fcaba93fa89c94e3357 /gas/config | |
| parent | a23b33b3d131f240b2525d9a24831b33f2b43e26 (diff) | |
| download | gdb-643bb87079dd96aed99ff1572375a88179afcd15.zip gdb-643bb87079dd96aed99ff1572375a88179afcd15.tar.gz gdb-643bb87079dd96aed99ff1572375a88179afcd15.tar.bz2 | |
x86: drop Rex64 attribute
It is almost entirely redundant with Size64, and the sole case (CRC32)
where direct replacement isn't possible can easily be taken care of in
another way.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-i386.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 1c9388b..9a26a1d 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -4567,9 +4567,6 @@ md_assemble (char *line) i.op[0].disps->X_op = O_symbol; } - if (i.tm.opcode_modifier.rex64) - i.rex |= REX_W; - /* For 8 bit registers we need an empty rex prefix. Also if the instruction already has a prefix, we need to convert old registers to new ones. */ @@ -6338,6 +6335,11 @@ process_suffix (void) || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64)) --i.operands; + /* crc32 needs REX.W set regardless of suffix / source operand size. */ + if (i.tm.base_opcode == 0xf20f38f0 + && i.tm.operand_types[1].bitfield.qword) + i.rex |= REX_W; + /* If there's no instruction mnemonic suffix we try to invent one based on GPR operands. */ if (!i.suffix) |