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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-05-16 12:05:34 +0100 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-05-16 16:36:50 +0100 |
| commit | 4aa88b50c4eec0256bcba33e02135f224a725d68 (patch) | |
| tree | da7bdea20a642d479e58921bd412e08cf2ed6956 /gas/config | |
| parent | 1be7aba392cd32a9a7165ecb4635c2733b5ac7ba (diff) | |
| download | gdb-4aa88b50c4eec0256bcba33e02135f224a725d68.zip gdb-4aa88b50c4eec0256bcba33e02135f224a725d68.tar.gz gdb-4aa88b50c4eec0256bcba33e02135f224a725d68.tar.bz2 | |
[PATCH 31/57][Arm][GAS] Add support for MVE instructions: vshrn[tb], vrshrn[tb], vqshrn[tb], vqshrun[tb], vqrshrn[tb] and vqrshrun[tb]
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vshrnt, M_MNEM_vshrnb, M_MNEM_vrshrnt,
M_MNEM_vqshrnt, M_MNEM_vqshrnb, M_MNEM_vqshrunt, M_MNEM_vqshrunb,
M_MNEM_vrshrnb, M_MNEM_vqrshrnt, M_MNEM_vqrshrnb, M_MNEM_vqrshrunt,
M_MNEM_vqrshrunb): New instruction encodings.
(do_mve_vshrn): New encoding function.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vqrshrn-bad.d: New test.
* testsuite/gas/arm/mve-vqrshrn-bad.l: New test.
* testsuite/gas/arm/mve-vqrshrn-bad.s: New test.
* testsuite/gas/arm/mve-vshrn-bad.d: New test.
* testsuite/gas/arm/mve-vshrn-bad.l: New test.
* testsuite/gas/arm/mve-vshrn-bad.s: New test.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-arm.c | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 0072ace..64e87db 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -14206,6 +14206,18 @@ do_t_loloop (void) #define M_MNEM_vqmovnb 0xee330e01 #define M_MNEM_vqmovunt 0xee311e81 #define M_MNEM_vqmovunb 0xee310e81 +#define M_MNEM_vshrnt 0xee801fc1 +#define M_MNEM_vshrnb 0xee800fc1 +#define M_MNEM_vrshrnt 0xfe801fc1 +#define M_MNEM_vqshrnt 0xee801f40 +#define M_MNEM_vqshrnb 0xee800f40 +#define M_MNEM_vqshrunt 0xee801fc0 +#define M_MNEM_vqshrunb 0xee800fc0 +#define M_MNEM_vrshrnb 0xfe800fc1 +#define M_MNEM_vqrshrnt 0xee801f41 +#define M_MNEM_vqrshrnb 0xee800f41 +#define M_MNEM_vqrshrunt 0xfe801fc0 +#define M_MNEM_vqrshrunb 0xfe800fc0 /* Neon instruction encoder helpers. */ @@ -15751,6 +15763,58 @@ do_mve_vmlas (void) } static void +do_mve_vshrn (void) +{ + unsigned types; + switch (inst.instruction) + { + case M_MNEM_vshrnt: + case M_MNEM_vshrnb: + case M_MNEM_vrshrnt: + case M_MNEM_vrshrnb: + types = N_I16 | N_I32; + break; + case M_MNEM_vqshrnt: + case M_MNEM_vqshrnb: + case M_MNEM_vqrshrnt: + case M_MNEM_vqrshrnb: + types = N_U16 | N_U32 | N_S16 | N_S32; + break; + case M_MNEM_vqshrunt: + case M_MNEM_vqshrunb: + case M_MNEM_vqrshrunt: + case M_MNEM_vqrshrunb: + types = N_S16 | N_S32; + break; + default: + abort (); + } + + struct neon_type_el et = neon_check_type (2, NS_QQI, N_EQK, types | N_KEY); + + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + unsigned Qd = inst.operands[0].reg; + unsigned Qm = inst.operands[1].reg; + unsigned imm = inst.operands[2].imm; + constraint (imm < 1 || ((unsigned) imm) > (et.size / 2), + et.size == 16 + ? _("immediate operand expected in the range [1,8]") + : _("immediate operand expected in the range [1,16]")); + + inst.instruction |= (et.type == NT_unsigned) << 28; + inst.instruction |= HI1 (Qd) << 22; + inst.instruction |= (et.size - imm) << 16; + inst.instruction |= LOW4 (Qd) << 12; + inst.instruction |= HI1 (Qm) << 5; + inst.instruction |= LOW4 (Qm); + inst.is_neon = 1; +} + +static void do_mve_vqmovn (void) { struct neon_type_el et; @@ -24946,6 +25010,19 @@ static const struct asm_opcode insns[] = mCEF(vqmovunt, _vqmovunt, 2, (RMQ, RMQ), mve_vqmovn), mCEF(vqmovunb, _vqmovunb, 2, (RMQ, RMQ), mve_vqmovn), + mCEF(vshrnt, _vshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vshrnb, _vshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vrshrnt, _vrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vrshrnb, _vrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqrshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqrshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqrshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqrshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn), + #undef THUMB_VARIANT #define THUMB_VARIANT & mve_fp_ext mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul), |