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author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 19:21:33 +0000 |
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committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 19:29:05 +0000 |
commit | 971eda734150ea9cdea47be259486c3a8d087037 (patch) | |
tree | 3b9493f052037ac3bde3619db1c4e7d22d986d0b /gas/config | |
parent | 57f02370a1e55bf09d3ede5ba6b2fcc78b40200a (diff) | |
download | gdb-971eda734150ea9cdea47be259486c3a8d087037.zip gdb-971eda734150ea9cdea47be259486c3a8d087037.tar.gz gdb-971eda734150ea9cdea47be259486c3a8d087037.tar.bz2 |
aarch64: [SME] Add SME instructions
Patch is adding new SME matrix instructions. Please note additional
instructions will be added in following patches.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sme_zada_operand):
New parser.
* config/tc-aarch64.c (parse_reg_with_qual):
New reg parser.
* config/tc-aarch64.c (R_ZA): New egister type.
(parse_operands): New parser.
* testsuite/gas/aarch64/sme-illegal.d: New test.
* testsuite/gas/aarch64/sme-illegal.l: New test.
* testsuite/gas/aarch64/sme-illegal.s: New test.
* testsuite/gas/aarch64/sme.d: New test.
* testsuite/gas/aarch64/sme.s: New test.
* testsuite/gas/aarch64/sme-f64.d: New test.
* testsuite/gas/aarch64/sme-f64.s: New test.
* testsuite/gas/aarch64/sme-i64.d: New test.
* testsuite/gas/aarch64/sme-i64.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New operands
AARCH64_OPND_SME_ZAda_2b, AARCH64_OPND_SME_ZAda_3b and
AARCH64_OPND_SME_Pm.
(enum aarch64_insn_class): New instruction class sme_misc.
opcodes/ChangeLog:
* aarch64-opc.c (aarch64_print_operand):
Print OPND_SME_ZAda_2b and OPND_SME_ZAda_3b operands.
(verify_constraints): Handle OPND_SME_Pm.
* aarch64-opc.h (enum aarch64_field_kind):
New bit fields FLD_SME_ZAda_2b, FLD_SME_ZAda_3b and FLD_SME_Pm.
* aarch64-tbl.h (OP_SME_ZADA_PN_PM_ZN_S): New qualifier set.
(OP_SME_ZADA_PN_PM_ZN_D): New qualifier.
(OP_SME_ZADA_PN_PM_ZN_ZM): New qualifier.
(OP_SME_ZADA_S_PM_PM_S_S): New qualifier.
(OP_SME_ZADA_D_PM_PM_D_D): New qualifier.
(OP_SME_ZADA_S_PM_PM_H_H): New qualifier.
(OP_SME_ZADA_S_PM_PM_B_B): New qualifier.
(OP_SME_ZADA_D_PM_PM_H_H): New qualifier.
(SME_INSN): New instruction macro.
(SME_F64_INSN): New instruction macro.
(SME_I64_INSN): New instruction macro.
(SME_INSNC): New instruction macro.
(struct aarch64_opcode): New SME instructions.
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
Diffstat (limited to 'gas/config')
-rw-r--r-- | gas/config/tc-aarch64.c | 127 |
1 files changed, 126 insertions, 1 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index b592e80..7c94e9b 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -278,6 +278,7 @@ struct reloc_entry BASIC_REG_TYPE(VN) /* v[0-31] */ \ BASIC_REG_TYPE(ZN) /* z[0-31] */ \ BASIC_REG_TYPE(PN) /* p[0-15] */ \ + BASIC_REG_TYPE(ZA) /* za[0-15] */ \ /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \ MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \ /* Typecheck: same, plus SVE registers. */ \ @@ -4164,6 +4165,117 @@ parse_bti_operand (char **str, return 0; } +/* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER. + Function returns REG_ENTRY struct and QUALIFIER [bhsdq] or NULL + on failure. Format: + + REG_TYPE.QUALIFIER + + Side effect: Update STR with current parse position of success. +*/ + +static const reg_entry * +parse_reg_with_qual (char **str, aarch64_reg_type reg_type, + aarch64_opnd_qualifier_t *qualifier) +{ + char *q; + + reg_entry *reg = parse_reg (str); + if (reg != NULL && reg->type == reg_type) + { + if (!skip_past_char (str, '.')) + { + set_syntax_error (_("missing ZA tile element size separator")); + return NULL; + } + + q = *str; + switch (TOLOWER (*q)) + { + case 'b': + *qualifier = AARCH64_OPND_QLF_S_B; + break; + case 'h': + *qualifier = AARCH64_OPND_QLF_S_H; + break; + case 's': + *qualifier = AARCH64_OPND_QLF_S_S; + break; + case 'd': + *qualifier = AARCH64_OPND_QLF_S_D; + break; + case 'q': + *qualifier = AARCH64_OPND_QLF_S_Q; + break; + default: + return NULL; + } + q++; + + *str = q; + return reg; + } + + return NULL; +} + +/* Parse SME ZA tile encoded in <ZAda> assembler symbol. + Function return tile QUALIFIER on success. + + Tiles are in example format: za[0-9]\.[bhsd] + + Function returns <ZAda> register number or PARSE_FAIL. +*/ +static int +parse_sme_zada_operand (char **str, aarch64_opnd_qualifier_t *qualifier) +{ + int regno; + const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_ZA, qualifier); + + if (reg == NULL) + return PARSE_FAIL; + regno = reg->number; + + switch (*qualifier) + { + case AARCH64_OPND_QLF_S_B: + if (regno != 0x00) + { + set_syntax_error (_("invalid ZA tile register number, expected za0")); + return PARSE_FAIL; + } + break; + case AARCH64_OPND_QLF_S_H: + if (regno > 0x01) + { + set_syntax_error (_("invalid ZA tile register number, expected za0-za1")); + return PARSE_FAIL; + } + break; + case AARCH64_OPND_QLF_S_S: + if (regno > 0x03) + { + /* For the 32-bit variant: is the name of the ZA tile ZA0-ZA3. */ + set_syntax_error (_("invalid ZA tile register number, expected za0-za3")); + return PARSE_FAIL; + } + break; + case AARCH64_OPND_QLF_S_D: + if (regno > 0x07) + { + /* For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 */ + set_syntax_error (_("invalid ZA tile register number, expected za0-za7")); + return PARSE_FAIL; + } + break; + default: + set_syntax_error (_("invalid ZA tile element size, allowed b, h, s and d")); + return PARSE_FAIL; + } + + return regno; +} + /* Parse a system register or a PSTATE field name for an MSR/MRS instruction. Returns the encoding for the option, or PARSE_FAIL. @@ -5801,6 +5913,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Pm: case AARCH64_OPND_SVE_Pn: case AARCH64_OPND_SVE_Pt: + case AARCH64_OPND_SME_Pm: reg_type = REG_TYPE_PN; goto vector_reg; @@ -6867,6 +6980,15 @@ parse_operands (char *str, const aarch64_opcode *opcode) goto failure; break; + case AARCH64_OPND_SME_ZAda_2b: + case AARCH64_OPND_SME_ZAda_3b: + val = parse_sme_zada_operand (&str, &qualifier); + if (val == PARSE_FAIL) + goto failure; + info->reg.regno = val; + info->qualifier = qualifier; + break; + default: as_fatal (_("unhandled operand code %d"), operands[i]); } @@ -7463,7 +7585,10 @@ static const reg_entry reg_names[] = { REGSET (z, ZN), REGSET (Z, ZN), /* SVE predicate registers. */ - REGSET16 (p, PN), REGSET16 (P, PN) + REGSET16 (p, PN), REGSET16 (P, PN), + + /* SME ZA tile registers. */ + REGSET16 (za, ZA), REGSET16 (ZA, ZA) }; #undef REGDEF |