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| author | Thiemo Seufer <ths@networkno.de> | 2008-11-28 18:02:17 +0000 |
|---|---|---|
| committer | Thiemo Seufer <ths@networkno.de> | 2008-11-28 18:02:17 +0000 |
| commit | 3aa3176b2dea5796ab968b289804eced655f07ee (patch) | |
| tree | ad2039e6910f4951a98b3def13d245d7197b2638 /gas/config | |
| parent | 6fce36a432ae0879f863bd5d942ae17a5e36d297 (diff) | |
| download | gdb-3aa3176b2dea5796ab968b289804eced655f07ee.zip gdb-3aa3176b2dea5796ab968b289804eced655f07ee.tar.gz gdb-3aa3176b2dea5796ab968b289804eced655f07ee.tar.bz2 | |
* aoutx.h (NAME): Add case statements for bfd_mach_mips14000,
bfd_mach_mips16000.
* archures.c (bfd_architecture): Add .#defines for bfd_mach_mips14000,
bfd_mach_mips16000.
* bfd-in2.h: Regenerate.
* cpu-mips.c: Add enums I_mips14000, I_mips16000.
(arch_info_struct): Add refs to R14000, R16000.
* elfxx-mips.c (mips_set_isa_flags): Handle bfd_mach_mips14000,
bfd_mach_mips16000.
(mips_mach_extensions): Map R14000, R16000 to R10000.
* config/tc-mips.c (hilo_interlocks): Handle CPU_R14000, CPU_R16000.
(mips_cpu_info_table): Add r14000, r16000.
* doc/c-mips.texi: Add entries for 14000, 16000.
* mips-dis.c (mips_arch_choices): Add r14000, r16000.
* mips.h: Define CPU_R14000, CPU_R16000.
(OPCODE_IS_MEMBER): Include R14000, R16000 in test.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-mips.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 17ee8d1..c472509 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -472,6 +472,8 @@ static int mips_32bitmode = 0; || mips_opts.arch == CPU_R4010 \ || mips_opts.arch == CPU_R10000 \ || mips_opts.arch == CPU_R12000 \ + || mips_opts.arch == CPU_R14000 \ + || mips_opts.arch == CPU_R16000 \ || mips_opts.arch == CPU_RM7000 \ || mips_opts.arch == CPU_VR5500 \ ) @@ -15090,6 +15092,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { "r8000", 0, ISA_MIPS4, CPU_R8000 }, { "r10000", 0, ISA_MIPS4, CPU_R10000 }, { "r12000", 0, ISA_MIPS4, CPU_R12000 }, + { "r14000", 0, ISA_MIPS4, CPU_R14000 }, + { "r16000", 0, ISA_MIPS4, CPU_R16000 }, { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, |