aboutsummaryrefslogtreecommitdiff
path: root/gas/config
diff options
context:
space:
mode:
authorH.J. Lu <hjl.tools@gmail.com>2007-08-28 17:36:34 +0000
committerH.J. Lu <hjl.tools@gmail.com>2007-08-28 17:36:34 +0000
commitd9a5e5e5c91086a8dd66174a7ebff52c00efe79e (patch)
treebd7ab2e401e44e7ee2b191527d4658d507c21533 /gas/config
parentd5ce5596bf611b65e4fc93b4e90df67359f4cba5 (diff)
downloadgdb-d9a5e5e5c91086a8dd66174a7ebff52c00efe79e.zip
gdb-d9a5e5e5c91086a8dd66174a7ebff52c00efe79e.tar.gz
gdb-d9a5e5e5c91086a8dd66174a7ebff52c00efe79e.tar.bz2
gas/
2007-08-28 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_suffix): Handle cmpxchg8b in Intel mode. gas/testsuite/ 2007-08-28 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/mem.s: New. Add tests for instructions with one memory operand. * gas/i386/x86-64-mem.s: Likewise. * gas/i386/mem-intel.d: Updated. * gas/i386/mem.d: Likewise. * gas/i386/x86-64-mem-intel.d: Likewise. * gas/i386/x86-64-mem.d: Likewise. opcodes/ 2007-08-28 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (Md): New. (grps): Use 0 on invlpg. Use M on fxsave and fxrstor. Use Md on ldmxcsr and stmxcsr. Use b_mode on clflush. (OP_0fae): Clear bytemode for sfence.
Diffstat (limited to 'gas/config')
-rw-r--r--gas/config/tc-i386.c16
1 files changed, 11 insertions, 5 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 16376dc..0f6396f 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3032,11 +3032,17 @@ process_suffix (void)
&& (i.tm.opcode_modifier & NoRex64) == 0)
{
/* Special case for xchg %rax,%rax. It is NOP and doesn't
- need rex64. */
- if (i.operands != 2
- || i.types [0] != (Acc | Reg64)
- || i.types [1] != (Acc | Reg64)
- || i.tm.base_opcode != 0x90)
+ need rex64. cmpxchg8b is also a special case. */
+ if (! (i.operands == 2
+ && i.tm.base_opcode == 0x90
+ && i.tm.extension_opcode == None
+ && i.types [0] == (Acc | Reg64)
+ && i.types [1] == (Acc | Reg64))
+ && ! (i.operands == 1
+ && i.tm.base_opcode == 0xfc7
+ && i.tm.extension_opcode == 1
+ && (i.types [0] & Reg) == 0
+ && (i.types [0] & AnyMem) != 0))
i.rex |= REX_W;
}