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authorCatherine Moore <clm@codesourcery.com>2013-11-11 08:03:47 -0800
committerCatherine Moore <clm@codesourcery.com>2013-11-11 08:03:47 -0800
commit67dc82bc511e35ef134952014b4deb2fdcf10676 (patch)
tree42bfe2316900f645cba2e3bab5ed60b2f8590e03 /gas/config
parent2df4d1d5c4393fd06c2bffe75499e70a8d8ac8a8 (diff)
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2013-11-11 Catherine Moore <clm@codesourcery.com>
gas/ * config/mips/tc-mips.c (convert_reg_type): Use INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY. (reg_needs_delay): Likewise. (insns_between): Likewise. include/ * opcode/mips.h (INSN_LOAD_MEMORY_DELAY): Rename to... (INSN_LOAD_MEMORY): ...this. opcodes/ * mips-dis.c (print_insn_mips): Use INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY. (print_insn_micromips): Likewise. * mips-opc.c (LDD): Remove. (CLD): Include INSN_LOAD_MEMORY. (LM): New. (mips_builtin_opcodes): Use LM instead of LDD. Add LM to load instructions.
Diffstat (limited to 'gas/config')
-rw-r--r--gas/config/tc-mips.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 08ad7ba..fcf06ac 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -491,7 +491,7 @@ static int mips_32bitmode = 0;
/* Whether the processor uses hardware interlocks to protect reads
from the GPRs after they are loaded from memory, and thus does not
require nops to be inserted. This applies to instructions marked
- INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
+ INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
level I and microMIPS mode instructions are always interlocked. */
#define gpr_interlocks \
(mips_opts.isa != ISA_MIPS1 \
@@ -4389,7 +4389,7 @@ convert_reg_type (const struct mips_opcode *opcode,
&& (opcode->pinfo & (INSN_COPROC_MOVE_DELAY
| INSN_COPROC_MEMORY_DELAY
| INSN_LOAD_COPROC_DELAY
- | INSN_LOAD_MEMORY_DELAY
+ | INSN_LOAD_MEMORY
| INSN_STORE_MEMORY)))
return RTYPE_FPU | RTYPE_VEC;
return RTYPE_FPU;
@@ -5529,7 +5529,7 @@ reg_needs_delay (unsigned int reg)
prev_pinfo = history[0].insn_mo->pinfo;
if (!mips_opts.noreorder
- && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) && !gpr_interlocks)
+ && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
|| ((prev_pinfo & INSN_LOAD_COPROC_DELAY) && !cop_interlocks))
&& (gpr_write_mask (&history[0]) & (1 << reg)))
return TRUE;
@@ -5633,7 +5633,7 @@ insns_between (const struct mips_cl_insn *insn1,
/* Check for GPR or coprocessor load delays. All such delays
are on the RT register. */
/* Itbl support may require additional care here. */
- if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
+ if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
|| (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
{
if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))