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author | Tamar Christina <tamar.christina@arm.com> | 2016-08-19 12:57:20 +0100 |
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committer | Nick Clifton <nickc@redhat.com> | 2016-08-19 12:58:49 +0100 |
commit | 873f10f02f5959ce9b74cc5b599f5006147de940 (patch) | |
tree | cc5f5385bddb342e589d152abff9868161c6e6af /gas/config | |
parent | 0646e07d6e88045d650ee1ec5b674da1cdeaa6b6 (diff) | |
download | gdb-873f10f02f5959ce9b74cc5b599f5006147de940.zip gdb-873f10f02f5959ce9b74cc5b599f5006147de940.tar.gz gdb-873f10f02f5959ce9b74cc5b599f5006147de940.tar.bz2 |
ARM: Issue a warning when the MRRC and MRRC2 instructions are used with the same destination registers.
* config/tc-arm.c (do_co_reg2c): Added constraint.
* testsuite/gas/arm/dest-unpredictable.s: New.
* testsuite/gas/arm/dest-unpredictable.l: New.
* testsuite/gas/arm/dest-unpredictable.d: New.
Diffstat (limited to 'gas/config')
-rw-r--r-- | gas/config/tc-arm.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index a8d9556..040fee4 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -8691,6 +8691,14 @@ do_co_reg2c (void) constraint (Rn == REG_PC, BAD_PC); } + /* Only check the MRRC{2} variants. */ + if ((inst.instruction & 0x0FF00000) == 0x0C500000) + { + /* If Rd == Rn, error that the operation is + unpredictable (example MRRC p3,#1,r1,r1,c4). */ + constraint (Rd == Rn, BAD_OVERLAP); + } + inst.instruction |= inst.operands[0].reg << 8; inst.instruction |= inst.operands[1].imm << 4; inst.instruction |= Rd << 12; |