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| author | Jan Beulich <jbeulich@novell.com> | 2005-01-31 08:48:32 +0000 |
|---|---|---|
| committer | Jan Beulich <jbeulich@novell.com> | 2005-01-31 08:48:32 +0000 |
| commit | 60b9a617725df23ea629c34a83919bf320082a7d (patch) | |
| tree | 41c516899c81c93b7ef9997355ee9e56e126c483 /gas/config | |
| parent | e901b190a91d42356660e45e459c60fac24b2e7d (diff) | |
| download | gdb-60b9a617725df23ea629c34a83919bf320082a7d.zip gdb-60b9a617725df23ea629c34a83919bf320082a7d.tar.gz gdb-60b9a617725df23ea629c34a83919bf320082a7d.tar.bz2 | |
gas/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (parse_operands): Also handle alloc without first
input being ar.pfs.
gas/testsuite/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* gas/ia64/pseudo.[ds]: New.
* gas/ia64/ia64.exp: Run new test.
opcodes/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* ia64-gen.c (NELEMS): Define.
(shrink): Generate alias with missing second predicate register when
opcode has two outputs and these are both predicates.
* ia64-opc-i.c (FULL17): Define.
(ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
here to generate output template.
(TBITCM, TNATCM): Undefine after use.
* ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
first input. Add ld16 aliases without ar.csd as second output. Add
st16 aliases without ar.csd as second input. Add cmpxchg aliases
without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
ar.ccv as third/fourth inputs. Consolidate through...
(CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
* ia64-asmtab.c: Regenerate.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-ia64.c | 36 |
1 files changed, 20 insertions, 16 deletions
diff --git a/gas/config/tc-ia64.c b/gas/config/tc-ia64.c index 21b62fb..6415647 100644 --- a/gas/config/tc-ia64.c +++ b/gas/config/tc-ia64.c @@ -5782,7 +5782,8 @@ parse_operands (idesc) assert (strlen (idesc->name) <= 128); strcpy (mnemonic, idesc->name); - if (idesc->operands[2] == IA64_OPND_SOF) + if (idesc->operands[2] == IA64_OPND_SOF + || idesc->operands[1] == IA64_OPND_SOF) { /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we can't parse the first operand until we have parsed the @@ -5825,20 +5826,23 @@ parse_operands (idesc) return 0; } - if (idesc->operands[2] == IA64_OPND_SOF) + if (idesc->operands[2] == IA64_OPND_SOF + || idesc->operands[1] == IA64_OPND_SOF) { /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */ know (strcmp (idesc->name, "alloc") == 0); - if (num_operands == 5 /* first_arg not included in this count! */ - && CURR_SLOT.opnd[2].X_op == O_constant - && CURR_SLOT.opnd[3].X_op == O_constant - && CURR_SLOT.opnd[4].X_op == O_constant - && CURR_SLOT.opnd[5].X_op == O_constant) - { - sof = set_regstack (CURR_SLOT.opnd[2].X_add_number, - CURR_SLOT.opnd[3].X_add_number, - CURR_SLOT.opnd[4].X_add_number, - CURR_SLOT.opnd[5].X_add_number); + i = (CURR_SLOT.opnd[1].X_op == O_register + && CURR_SLOT.opnd[1].X_add_number == REG_AR + AR_PFS) ? 2 : 1; + if (num_operands == i + 3 /* first_arg not included in this count! */ + && CURR_SLOT.opnd[i].X_op == O_constant + && CURR_SLOT.opnd[i + 1].X_op == O_constant + && CURR_SLOT.opnd[i + 2].X_op == O_constant + && CURR_SLOT.opnd[i + 3].X_op == O_constant) + { + sof = set_regstack (CURR_SLOT.opnd[i].X_add_number, + CURR_SLOT.opnd[i + 1].X_add_number, + CURR_SLOT.opnd[i + 2].X_add_number, + CURR_SLOT.opnd[i + 3].X_add_number); /* now we can parse the first arg: */ saved_input_pointer = input_line_pointer; @@ -5848,10 +5852,10 @@ parse_operands (idesc) --num_outputs; /* force error */ input_line_pointer = saved_input_pointer; - CURR_SLOT.opnd[2].X_add_number = sof; - CURR_SLOT.opnd[3].X_add_number - = sof - CURR_SLOT.opnd[4].X_add_number; - CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5]; + CURR_SLOT.opnd[i].X_add_number = sof; + CURR_SLOT.opnd[i + 1].X_add_number + = sof - CURR_SLOT.opnd[i + 2].X_add_number; + CURR_SLOT.opnd[i + 2] = CURR_SLOT.opnd[i + 3]; } } |