bfd:

	Add ms2.
	* archures.c (bfd_mach_ms2): Define.
	* cpu-ms1.c (arch_info_struct): Add ms2 stanza.
	* elf32-ms1.c (elf32_ms1_machine): Add ms2 case.
	(ms1_elf_merge_private_bfd_data): Remove unused variables.  Add
	correct merging logic, with workaround.
	(ms1_elf_print_private_bfd_data): Add ms2 case.
	* reloc.c (BFD_RELOC_MS1_PCINSN8): Add ms2 specific reloc.
	* libbfd.h: Regenerated.
	* bfd-in2.h: Regenerated.

cpu:
	Add ms2
	* ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
	model.
	(f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
	f-cb2incr, f-rc3): New fields.
	(LOOP): New instruction.
	(JAL-HAZARD): New hazard.
	(imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
	New operands.
	(mul, muli, dbnz, iflush): Enable for ms2
	(jal, reti): Has JAL-HAZARD.
	(ldctxt, ldfb, stfb): Only ms1.
	(fbcb): Only ms1,ms1-003.
	(wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
	fbcbincrs, mfbcbincrs): Enable for ms2.
	(loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
	* ms1.opc (parse_loopsize): New.
	(parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
	(print_pcrel): New.

gas:
	Add ms2.
	* config/tc-ms1.c (ms1_mach_bitmask): Initialize to MS1.
	(ms1_architectures): Add ms2.
	(md_parse_option): Add ms2.
	(md_show_usage): Add ms2.
	(md_assemble): Add JAL_HAZARD detection logic.
	(md_cgen_lookup_reloc): Add MS1_OPERAND_LOOPSIZE case.
	* doc/c-ms1.texi: New.
	* doc/all.texi: Add MS1.
	* doc/Makefile.am (CPU_DOCS): Add c-ms1.texi.
	* doc/Makefile.in: Rebuilt.
	* doc/Makefile: Rebuilt.

gas/testsuite:
	Add ms2.
	* gas/ms1/allinsn.d: Adjust pcrel disassembly.
	* gas/ms1/errors.exp: Fix target triplet.
	* gas/ms1/ms1-16-003.d: Adjust pcrel disassembly.
	* gas/ms1/ms1-16-003.s: Tweak label.
	* gas/ms1/ms1.exp: Adjust target triplet.  Add ms2 test.
	* gas/ms1/ms2.d, gas/ms1/ms2.s: New.
	* gas/ms1/relocs.d: Adjust expected machine name and pcrel
	disassembly.
	* gas/ms1/relocs.exp: Adjust target triplet.

include:
	Add ms2.
	* elf/ms1.h (EF_MS1_CPU_MS2): New.


opcodes:
	Add ms2.
	* ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c,
	ms1-opc.c, ms1-opc.h: Regenerated.

1 files changed, 38 insertions, 2 deletions

diff --git a/gas/config/tc-ms1.c b/gas/config/tc-ms1.c
index e459bc8..7e2e685 100644
--- a/gas/config/tc-ms1.c
+++ b/gas/config/tc-ms1.c
@@ -84,7 +84,7 @@ const char * md_shortopts = "";
 
 /* Mach selected from command line.  */
 static int ms1_mach = bfd_mach_ms1;
-static unsigned ms1_mach_bitmask = 0;
+static unsigned ms1_mach_bitmask = 1 << MACH_MS1;
 
 /* Flags to set in the elf header */
 static flagword ms1_flags = EF_MS1_CPU_MRISC;
@@ -94,7 +94,8 @@ enum ms1_architectures
   {
     ms1_64_001,
     ms1_16_002,
-    ms1_16_003
+    ms1_16_003,
+    ms2
   };
 
 /* MS1 architecture we are using for this output file.  */
@@ -127,6 +128,13 @@ md_parse_option (int c ATTRIBUTE_UNUSED, char * arg)
  	  ms1_mach_bitmask = 1 << MACH_MS1_003;
  	  ms1_arch = ms1_16_003;
  	}
+      else if (strcasecmp (arg, "MS2") == 0)
+ 	{
+ 	  ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MS2;
+ 	  ms1_mach = bfd_mach_mrisc2;
+ 	  ms1_mach_bitmask = 1 << MACH_MS2;
+ 	  ms1_arch = ms2;
+ 	}
     case OPTION_NO_SCHED_REST:
       no_scheduling_restrictions = 1;
       break;
@@ -145,6 +153,7 @@ md_show_usage (FILE * stream)
   fprintf (stream, _("  -march=ms1-64-001         allow ms1-64-001 instructions (default) \n"));
   fprintf (stream, _("  -march=ms1-16-002         allow ms1-16-002 instructions \n"));
   fprintf (stream, _("  -march=ms1-16-003         allow ms1-16-003 instructions \n"));
+  fprintf (stream, _("  -march=ms2                allow ms2 instructions \n"));
   fprintf (stream, _("  -nosched                  disable scheduling restrictions \n"));
 }
 
@@ -176,6 +185,7 @@ void
 md_assemble (char * str)
 {
   static long delayed_load_register = 0;
+  static long prev_delayed_load_register = 0;
   static int last_insn_had_delay_slot = 0;
   static int last_insn_in_noncond_delay_slot = 0;
   static int last_insn_has_load_delay = 0;
@@ -241,6 +251,24 @@ md_assemble (char * str)
 		     insn.fields.f_sr2);
 	}
 
+      /* Detect JAL/RETI hazard */
+      if (ms1_mach == ms2
+	  && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_JAL_HAZARD))
+	{
+	  if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
+	       && insn.fields.f_sr1 == delayed_load_register)
+	      || (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
+		  && insn.fields.f_sr2 == delayed_load_register))
+	    as_warn (_("operand references R%ld of previous instrutcion."),
+		     delayed_load_register);
+	  else if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
+		    && insn.fields.f_sr1 == prev_delayed_load_register)
+		   || (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
+		       && insn.fields.f_sr2 == prev_delayed_load_register))
+	    as_warn (_("operand references R%ld of instructcion before previous."),
+		     prev_delayed_load_register);
+	}
+      
       /* Detect data dependency between conditional branch instruction
          and an immediately preceding arithmetic or logical instruction.  */
       if (last_insn_was_arithmetic_or_logic
@@ -287,6 +315,8 @@ md_assemble (char * str)
   CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN)
     && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2);
   
+  prev_delayed_load_register = delayed_load_register;
+  
   if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDR))
      delayed_load_register = insn.fields.f_dr; 
   else if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDRRR))
@@ -381,6 +411,12 @@ md_cgen_lookup_reloc (const CGEN_INSN *    insn     ATTRIBUTE_UNUSED,
         result = fixP->fx_cgen.opinfo;
       fixP->fx_no_overflow = 1;
       break;
+    case MS1_OPERAND_LOOPSIZE:
+      result = BFD_RELOC_MS1_PCINSN8;
+      fixP->fx_pcrel = 1;
+      /* Adjust for the delay slot, which is not part of the loop  */
+      fixP->fx_offset -= 8;
+      break;
     default:
       result = BFD_RELOC_NONE;
       break;