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| author | claziss <claziss@synopsys.com> | 2017-06-07 15:57:56 +0200 |
|---|---|---|
| committer | claziss <claziss@synopsys.com> | 2017-06-26 08:53:10 +0200 |
| commit | cf9bdae906f897ae13563c03c65f325cad05bf1c (patch) | |
| tree | d4dd74a8a6e8da7955fb097844c91227f9bbe0b8 /gas/config | |
| parent | 46adbd17408fda28aca5320e2247ede30b7e9649 (diff) | |
| download | gdb-cf9bdae906f897ae13563c03c65f325cad05bf1c.zip gdb-cf9bdae906f897ae13563c03c65f325cad05bf1c.tar.gz gdb-cf9bdae906f897ae13563c03c65f325cad05bf1c.tar.bz2 | |
Update check conditions for illegal placed instructions.
ARC cpus do not accept any jump or instructions with long immediate
into the delay slots.
gas/
2017-06-07 Claudiu Zissulescu <claziss@synopsys.com>
* /config/tc-arc.c (is_br_jmp_insn_p): Update macro with known
instructions to be accounted as jumps.
(assemble_insn): Check for limms into the delay slots. Emit an
error if so.
* testsuite/gas/arc/asm-errors-3.d: New file.
* testsuite/gas/arc/asm-errors-3.err: Likewise.
* testsuite/gas/arc/asm-errors-3.s: Likewise.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-arc.c | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c index a56b2a5..dd67d77 100644 --- a/gas/config/tc-arc.c +++ b/gas/config/tc-arc.c @@ -107,8 +107,18 @@ enum arc_rlx_types #define is_spfp_p(op) (((sc) == SPX)) #define is_dpfp_p(op) (((sc) == DPX)) #define is_fpuda_p(op) (((sc) == DPA)) -#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \ - || (op)->insn_class == JUMP)) +#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \ + || (op)->insn_class == JUMP \ + || (op)->insn_class == BRCC \ + || (op)->insn_class == BBIT0 \ + || (op)->insn_class == BBIT1 \ + || (op)->insn_class == BI \ + || (op)->insn_class == EI \ + || (op)->insn_class == ENTER \ + || (op)->insn_class == JLI \ + || (op)->insn_class == LOOP \ + || (op)->insn_class == LEAVE \ + )) #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL)) #define is_nps400_p(op) (((sc) == NPS400)) @@ -4107,6 +4117,11 @@ assemble_insn (const struct arc_opcode *opcode, as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."), arc_last_insns[1].opcode->name, arc_last_insns[0].opcode->name); + if (arc_last_insns[1].has_delay_slot + && arc_last_insns[0].has_limm) + as_bad (_("Insn %s has an instruction %s with limm in its delay slot."), + arc_last_insns[1].opcode->name, + arc_last_insns[0].opcode->name); } void |