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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:13 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:13 +0100 |
| commit | ed429b33c1ee8d6d8f8e640e58f04ec800bc7b2a (patch) | |
| tree | 9dec9ddf10c70e8d8c16f5f0820eb23eefe4a733 /gas/config | |
| parent | 80752eb0989b85e88af7f1f4627dbed8a42dfe6d (diff) | |
| download | gdb-ed429b33c1ee8d6d8f8e640e58f04ec800bc7b2a.zip gdb-ed429b33c1ee8d6d8f8e640e58f04ec800bc7b2a.tar.gz gdb-ed429b33c1ee8d6d8f8e640e58f04ec800bc7b2a.tar.bz2 | |
aarch64: Add the SME2 MLAL and MLSL instructions
The {BF,F,S,U}MLAL and {BF,F,S,U}MLSL instructions share the same
encoding. They are the first instance of a ZA (as opposed to ZA tile)
operand having a range of offsets. As with ZA tiles, the expected
range size is encoded in the operand-specific data field.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-aarch64.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 47ad704..2aa3838 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6729,6 +6729,8 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Zn_INDEX: case AARCH64_OPND_SME_Zm_INDEX1: case AARCH64_OPND_SME_Zm_INDEX2: + case AARCH64_OPND_SME_Zm_INDEX3_2: + case AARCH64_OPND_SME_Zm_INDEX3_10: case AARCH64_OPND_SME_Zn_INDEX1_16: case AARCH64_OPND_SME_Zn_INDEX2_15: case AARCH64_OPND_SME_Zn_INDEX2_16: @@ -7850,8 +7852,10 @@ parse_operands (char *str, const aarch64_opcode *opcode) info->imm.value = val; break; + case AARCH64_OPND_SME_ZA_array_off2x2: case AARCH64_OPND_SME_ZA_array_off3_0: case AARCH64_OPND_SME_ZA_array_off3_5: + case AARCH64_OPND_SME_ZA_array_off3x2: case AARCH64_OPND_SME_ZA_array_off4: if (!parse_dual_indexed_reg (&str, REG_TYPE_ZA, &info->indexed_za, &qualifier, 0)) |