x86: fold certain AVX2 templates into their AVX counterparts

Like for AVX512VL we can make the handling of operand sizes a little
more flexible to allow reducing the number of templates we have.

1 files changed, 23 insertions, 0 deletions

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 8ef71b6..10eb0a3 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1963,6 +1963,12 @@ cpu_flags_match (const insn_template *t)
 	return match;
       x.bitfield.cpuavx512vl = 0;
 
+      /* AVX and AVX2 present at the same time express an operand size
+	 dependency - strip AVX2 for the purposes here.  The operand size
+	 dependent check occurs in check_vecOperands().  */
+      if (x.bitfield.cpuavx && x.bitfield.cpuavx2)
+	x.bitfield.cpuavx2 = 0;
+
       cpu = cpu_flags_and (x, cpu);
       if (!cpu_flags_all_zero (&cpu))
 	{
@@ -5993,6 +5999,23 @@ check_VecOperands (const insn_template *t)
 	}
     }
 
+  /* Somewhat similarly, templates specifying both AVX and AVX2 are
+     requiring AVX2 support if the actual operand size is YMMword.  */
+  if (t->cpu_flags.bitfield.cpuavx
+      && t->cpu_flags.bitfield.cpuavx2
+      && !cpu_arch_flags.bitfield.cpuavx2)
+    {
+      for (op = 0; op < t->operands; ++op)
+	{
+	  if (t->operand_types[op].bitfield.xmmword
+	      && i.types[op].bitfield.ymmword)
+	    {
+	      i.error = unsupported;
+	      return 1;
+	    }
+	}
+    }
+
   /* Without VSIB byte, we can't have a vector register for index.  */
   if (!t->opcode_modifier.sib
       && i.index_reg