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authorJoseph Myers <joseph@codesourcery.com>2009-01-29 11:48:34 +0000
committerJoseph Myers <joseph@codesourcery.com>2009-01-29 11:48:34 +0000
commit087b80de6eb85d50f0e936709c804647d7084770 (patch)
tree72bf69c06e322187ac59fbfd35bc44cf6ffc4b65 /gas/config
parent17828f45df981ed69e1e9a8eb2e5ec72cd0efbfe (diff)
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gas:
2009-01-29 Mark Mitchell <mark@codesourcery.com> * config/tc-arm.c (insns): Correct encoding of qadd, qdadd, qsub, qdsub in Thumb-2 mode. gas/testsuite: 2009-01-29 Mark Mitchell <mark@codesourcery.com> * gas/arm/thumb32.s (qadd): Add qadd, qdadd, qsub, and qdsub. * gas/arm/thumb32.d: Likewise. opcodes: 2009-01-29 Mark Mitchell <mark@codesourcery.com> * arm-dis.c (thumb32_opcodes): Correct decoding for qadd, qdadd, qsub, and qdsub.
Diffstat (limited to 'gas/config')
-rw-r--r--gas/config/tc-arm.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index f7bca73..0d4d005 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -15232,10 +15232,10 @@ static const struct asm_opcode insns[] =
TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
- TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
- TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
- TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
- TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
+ TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd),
+ TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd),
+ TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd),
+ TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd),
#undef ARM_VARIANT
#define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */