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| author | Kito Cheng <kito.cheng@gmail.com> | 2017-03-07 18:15:02 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-03-15 07:47:52 -0700 |
| commit | b416fe873ef44b2a613c9266c6462a481926d986 (patch) | |
| tree | 508c7f088305d110f17dd84951738a17314a7722 /gas/config | |
| parent | 03b039a518fa0f89a9900a44a8b874cc91061305 (diff) | |
| download | gdb-b416fe873ef44b2a613c9266c6462a481926d986.zip gdb-b416fe873ef44b2a613c9266c6462a481926d986.tar.gz gdb-b416fe873ef44b2a613c9266c6462a481926d986.tar.bz2 | |
RISC-V: Fix assembler for c.li, c.andi and c.addiw
- They can accept 0 in imm field
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
<c.andi>: Likewise.
<c.addiw> Likewise.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-riscv.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 79211f3..ff6d737 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -506,6 +506,7 @@ validate_riscv_insn (const struct riscv_opcode *opc) case 'c': break; /* RS1, constrained to equal sp */ case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break; case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break; + case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break; case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break; case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break; case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break; @@ -1327,6 +1328,13 @@ rvc_imm_done: ip->insn_opcode |= ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number); goto rvc_imm_done; + case 'o': + if (my_getSmallExpression (imm_expr, imm_reloc, s, p) + || imm_expr->X_op != O_constant + || !VALID_RVC_IMM (imm_expr->X_add_number)) + break; + ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); + goto rvc_imm_done; case 'K': if (my_getSmallExpression (imm_expr, imm_reloc, s, p) || imm_expr->X_op != O_constant |