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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2022-11-14 16:47:22 +0000 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2022-11-14 16:47:22 +0000 |
| commit | 1f7b42d52a8cb690c259eaa4975a608e82d7267a (patch) | |
| tree | 8e0d1faeeb5f8cfb1cf2caf218936c625ac46e98 /gas/config | |
| parent | 255571cdbf05213cc96feefb779c4158df453398 (diff) | |
| download | gdb-1f7b42d52a8cb690c259eaa4975a608e82d7267a.zip gdb-1f7b42d52a8cb690c259eaa4975a608e82d7267a.tar.gz gdb-1f7b42d52a8cb690c259eaa4975a608e82d7267a.tar.bz2 | |
aarch64: Add support for Common Short Sequence Compression extension
This patch adds support for the CSSC extension and its corresponding
instructions: ABS, CNT, CTZ, SMAX, UMAX, SMIN, UMIN.
gas/ChangeLog:
* config/tc-aarch64.c (parse_operands): Handle new operand types.
* doc/c-aarch64.texi: Document new extension.
* testsuite/gas/aarch64/cssc.d: New test.
* testsuite/gas/aarch64/cssc.s: New test.
include/ChangeLog:
* opcode/aarch64.h (AARCH64_FEATURE_CSSC): New feature Macro.
(enum aarch64_opnd): New operand types.
(enum aarch64_insn_class): New instruction class.
opcodes/ChangeLog:
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (operand_general_constraint_met_p): Update for new
operand types.
(aarch64_print_operand): Likewise.
* aarch64-opc.h (enum aarch64_field_kind): Declare FLD_CSSC_imm8 field.
* aarch64-tbl.h (aarch64_feature_cssc): Define new feature set.
(CSSC): Define new feature set Macro.
(CSSC_INSN): Define new instruction type.
(aarch64_opcode_table): Add new instructions.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-aarch64.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index f6fa158..165d927 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6636,6 +6636,8 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_IMM_ROT1: case AARCH64_OPND_SVE_IMM_ROT2: case AARCH64_OPND_SVE_IMM_ROT3: + case AARCH64_OPND_CSSC_SIMM8: + case AARCH64_OPND_CSSC_UIMM8: po_imm_nc_or_fail (); info->imm.value = val; break; @@ -10041,6 +10043,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { AARCH64_ARCH_NONE}, {"hbc", AARCH64_FEATURE (AARCH64_FEATURE_HBC, 0), AARCH64_ARCH_NONE}, + {"cssc", AARCH64_FEATURE (AARCH64_FEATURE_CSSC, 0), + AARCH64_ARCH_NONE}, {NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE}, }; |