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authorNick Clifton <nickc@redhat.com>2018-02-13 16:50:04 +0000
committerNick Clifton <nickc@redhat.com>2018-02-13 16:50:04 +0000
commitdb7bf1058d28b2b5e931c60435a13f6db15df6af (patch)
tree2ea78fb333faf39121c7d1195b2feaed39b3ddd5 /gas/config
parentbd7ab16b4537788ad53521c45469a1bdae84ad4a (diff)
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Fix ARm assembler so that it rejects invalid immediate values for the Thumb ORR instruction.
PR 22773 * config/tc-arm.c (md_apply_fix): Test Rn field of Thumb ORR instruction before assuming that it is a MOV instruction. * testsuite/gas/arm/pr22773.s: New test. * testsuite/gas/arm/pr22773.d: New test driver. * testsuite/gas/arm/pr22773.l: New expected output.
Diffstat (limited to 'gas/config')
-rw-r--r--gas/config/tc-arm.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 9786f14..7a5c02b 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -23596,12 +23596,14 @@ md_apply_fix (fixS * fixP,
/* MOV accepts both Thumb2 modified immediate (T2 encoding) and
UINT16 (T3 encoding), MOVW only accepts UINT16. When
disassembling, MOV is preferred when there is no encoding
- overlap.
- NOTE: MOV is using ORR opcode under Thumb 2 mode. */
+ overlap. */
if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR
+ /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
+ but with the Rn field [19:16] set to 1111. */
+ && (((newval >> 16) & 0xf) == 0xf)
&& ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)
&& !((newval >> T2_SBIT_SHIFT) & 0x1)
- && value >= 0 && value <=0xffff)
+ && value >= 0 && value <= 0xffff)
{
/* Toggle bit[25] to change encoding from T2 to T3. */
newval ^= 1 << 25;