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author | Ben Elliston <bje@au.ibm.com> | 2005-01-31 23:18:35 +0000 |
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committer | Ben Elliston <bje@au.ibm.com> | 2005-01-31 23:18:35 +0000 |
commit | 65ec77d24561f693faed3798a7233bc4f947a6b8 (patch) | |
tree | 280379ddd681847093ca04665aef1212573d1d16 /gas/config/xtensa-relax.c | |
parent | 0e71e4955cd1a6ad7d03775dec5df49323204dec (diff) | |
download | gdb-65ec77d24561f693faed3798a7233bc4f947a6b8.zip gdb-65ec77d24561f693faed3798a7233bc4f947a6b8.tar.gz gdb-65ec77d24561f693faed3798a7233bc4f947a6b8.tar.bz2 |
* config/atof-ieee.c, config/obj-coff.c, config/obj-elf.c,
config/obj-ieee.c, config/obj-som.c, config/obj-vms.c,
config/tc-a29k.c, config/tc-alpha.c, config/tc-arc.c,
config/tc-arm.c, config/tc-d30v.c, config/tc-dlx.c,
config/tc-fr30.c, config/tc-h8300.c, config/tc-h8500.c,
config/tc-i370.c, config/tc-i386.c, config/tc-i960.c,
config/tc-ia64.c, config/tc-m32r.c, config/tc-m32r.h,
config/tc-m68hc11.c, config/tc-m68hc11.h, config/tc-mips.c,
config/tc-mn10200.c, config/tc-msp430.c, config/tc-ns32k.c,
config/tc-openrisc.c, config/tc-or32.c, config/tc-pdp11.c,
config/tc-pj.c, config/tc-sparc.h, config/tc-tic54x.c,
config/tc-tic80.c, config/tc-v850.c, config/tc-w65.c,
config/tc-xtensa.c, config/tc-z8k.c, config/xtensa-relax.c: Remove
#if 0'd code throughout.
Diffstat (limited to 'gas/config/xtensa-relax.c')
-rw-r--r-- | gas/config/xtensa-relax.c | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/gas/config/xtensa-relax.c b/gas/config/xtensa-relax.c index d54a55c..f4663e7 100644 --- a/gas/config/xtensa-relax.c +++ b/gas/config/xtensa-relax.c @@ -299,15 +299,6 @@ static string_pattern_pair widen_spec_list[] = {"l32i %at,%as,%imm | %at!=%as ? IsaUseConst16", "const16 %at,HI16U(%imm); const16 %at,LOW16U(%imm); add %at,%at,%as; l32i %at,%at,0"}, -#if 0 /* Xtensa Synchronization Option not yet available */ - {"l32ai %at,%as,%imm ? IsaUseL32R", - "LITERAL0 %imm; l32r %at,%LITERAL0; add.n %at,%at,%as; l32ai %at,%at,0"}, -#endif -#if 0 /* Xtensa Speculation Option not yet available */ - {"l32is %at,%as,%imm ? IsaUseL32R", - "LITERAL0 %imm; l32r %at,%LITERAL0; add.n %at,%at,%as; l32is %at,%at,0"}, -#endif - /* This is only PART of the loop instruction. In addition, hardcoded into its use is a modification of the final operand in the instruction in bytes 9 and 12. */ @@ -1545,10 +1536,6 @@ build_transition (insn_pattern *initial_insn, if (opcode == XTENSA_UNDEFINED) { /* It is OK to not be able to translate some of these opcodes. */ -#if 0 - as_warn (_("invalid opcode '%s' in transition rule '%s'"), - initial_insn->t.opcode_name, from_string); -#endif return NULL; } @@ -1559,12 +1546,6 @@ build_transition (insn_pattern *initial_insn, /* This is also OK because there are opcodes that have different numbers of operands on different architecture variations. */ -#if 0 - as_fatal (_("opcode %s mismatched operand count %d != expected %d"), - xtensa_opcode_name (isa, opcode), - xtensa_num_operands (isa, opcode), - insn_templ_operand_count (&initial_insn->t)); -#endif return NULL; } |